Sandflat

SandFlat - low-cost FPGA/DSP platform

SandFlat is an open-hardware development board based on our SoldierCrab M.2 FPGA SoM. Its primary goal is similar to Tiliqua in that it aims to be a an audio and video DSP experimentation platform - however, compared to Tiliqua, SandFlat has less features, is a bare board, and can be manufactured much more cheaply (around $40-50 for both the SoM and SandFlat together in reasonable quantities). This makes a different set of tradeoffs to Tiliqua.

The main difference is that there are no audio CODECs or audio frontend on SandFlat. These can be added with PMODs on one of the 4 expansion connectors (e.g. our own eurorack-pmod). Crucially, no additional hardware is needed to play with audio DSP in hardware on SandFlat, as you can stream audio straight into / out of your computer/DAW using the high-speed USB2 port. All you need is the SandFlat board and a computer.

Features

• SoldierCrab FPGA SoM:
  • LFE5U-25: 25K LUT ECP5 FPGA
  • APS256XXN: 32MiB PSRAM (400MT/sec)
  • USB2 high-speed PHY: 480mbit/sec
• SandFlat board itself:
  • 1x USB FS for power in and RP2350 for debugging / usb-serial
    • RP2350 has 8 GPIOs shared with one of the PMOD expansion ports for a wide FPGA <-> MCU bus.
  • 1x USB2 dual-role device + host port, TUSB322I USB-C controller IC
  • 4x 8-pin PMOD-compatible expansion ports
  • Digital video output with DVI redriver for solid EMC / long cable performance
    • EDID is exposed + level translated so display timings can be read

Example gateware

This repository contains a few example projects which run on SandFlat:

• src/top/blink.py: Simplest example blinking the SoldierCrab LEDs
• src/top/dsp.py: DSP examples based on Tiliqua's DSP library, streaming all audio in/out the USB2 port.
• src/top/colorbar.py: Video example showing color bars at 640x480p60
• src/top/vectorscope.py: Vectorscope example taking audio from a USB stream and rendering it to a framebuffer in PSRAM out over video.
• FUTURE: it would be nice to port over one of the SoC projects from Tiliqua to SandFlat.

Building / flashing

A freshly manufactured SandFlat first needs pico-dirtyJtag flashed to the RP2350. - A working version is available on this branch of my pico-dirtyJtag fork.

Once your RP2350 is bootstrapped, you should be able to see the ECP5 with openFPGALoader:

$ openFPGALoader -c dirtyJtag --detect

Now, you can build one of the examples. After installing PDM, install all the dependencies and build a bitstream:

pdm install
pdm dsp build --core=mirror

This will synthesize a build/top.bit which enumerates as a USB2 audio device which sends all input audio (computer loudspeaker out) back out to the outputs (computer mic in). To flash it to the FPGA:

$ openFPGALoader -c dirtyJtag build/top.bit

Note: this will not persist unless you write it to flash permanently with -f.

Tips

• For the USB audio examples, ensure Audacity or your chosen audio program is playing AND recording audio at the same time, as the output stream is gated on the clock of the input stream (this behaviour could be changed in gateware, it's just something to be careful of).
• For the dual-role USB2 port: suggest always using a USB-A to USB-C cable -- as the example gateware doesn't configure the TUSB322I USB-C controller chip, (you probably want a whole SoC/CPU to do this, as Tiliqua does - I don't have examples of this yet)

Hardware status / bugs

Design files for R1.0 of the hardware are in hardware/. This version has been brought up and is largely working, with a couple of minor bugs found:

• Input current enumeration - the device port enumerates 500mA current required, but if SandFlat is used as a USB host, some devices may cause the board to draw more than 500mA -> we should instead be enumerating 1A on the debug port.
• Applying power to the dual-role usb2 port while unplugging the debug port may cause the 3V3 switchmode to start oscillating / leaking -> this can be fixed by adding a 1kOhm resistor across the 5V rail, and should be rolled into the next revision.
• The RP2350 bridge resistors to the I2C bus should be removed if using the pico-dirtyJtag modifications above -> this version seems to pull the I2C bus down and stops the external PLL from being addressable.

Building / Availability

• Production files and KiCAD projects for manufacturing or modifying SandFlat can be found in the hardware/folder.
• KiCAD projects for the SoldierCrab SoM are available here. It is also available on Crowd Supply.

SandFlat is not generally available yet, however if you are interested in trying it out, feel free to email me, I may have a few prototypes to spare.

Updates / Community

For updates, join the matrix chatroom, or my own mailing list.

Participants in this project are expected to adhere to the Berlin Code of Conduct.

Acknowledgements

We would like to acknowledge partial funding of the Tiliqua project from the NGI Commons Fund, a fund established by NLnet with financial support from the European Commission’s Next Generation Internet program.

License

The hardware and gateware in this project is largely covered under the CERN Open-Hardware License V2 CERN-OHL-S, mirrored in the LICENSE text in this repository. Some gateware and software is covered under the BSD 3-clause license - check the header of the individual source files for specifics.