Esp32c3-sensor node

ESP32-C3 environmental sensor node: KiCad 10 PCB

A 50 × 40 mm, 2-layer Wi-Fi/BLE temperature and humidity sensor board, powered and programmed over USB-C. It carries an ESP32-C3-WROOM-02 module and a Sensirion SHT40 sensor, plus USB-C input protection and a 3.3 V LDO. The schematic and the PCB are both generated from one Python description (scripts/design.py) through KiCad's file formats and pcbnew API, routed with Freerouting and verified with KiCad's own checks:

Top (3D render)	Bottom

The board fits the 3D-printed enclosure in freecad-parametric-parts. That enclosure is generated from this board's placement, and its pipeline checks the base and lid for interference against the STEP model exported from this PCB.

Circuit

Schematic (PDF) · SVG

Layout

• 2 layers, 1.6 mm: signals mostly on F.Cu, a GND pour on both layers tied together by 125 stitching vias, 179 track segments (343 mm), 12 signal vias.
• Antenna: the module sits on the top edge with its antenna over a copper-free keep-out (Espressif's recommended clearance, taken from the footprint's rule area).
• Thermal isolation of the sensor: the SHT40 sits in the corner furthest from the LDO, behind a 1 mm milled slot that blocks heat conduction from the module. The footprint keeps copper out from under the sensing die.
• USB: the D+/D− pads interleave on a 0.5 mm pitch (B7 D−, A6 D+, A7 D−, B6 D+), so the USB net class uses 0.2 mm tracks with 0.15 mm clearance and 0.45/0.2 mm vias to cross the pairs.
• Net classes (in scripts/project.kicad_pro): Default 0.2 mm, Power 0.3 mm, USB 0.2 mm; minimum track/space 0.15 mm, minimum drill 0.2 mm (also needed by the module's thermal vias). This is within standard 2-layer service at JLCPCB and PCBWay.
• Reference designators go on the Fab layer to keep the silkscreen clean. RST/BOOT are labelled on top, and the board name and revision are on the back.

Top copper	Bottom copper (mirrored)

Manufacturing files

fab/ holds everything needed to order the board and have it assembled:

How it is built

scripts/design.py        parts, footprints, pin -> net map, schematic positions, PCB placement
scripts/gen_schematic.py writes the .kicad_sch: symbols embedded from the KiCad 10 libraries, a wire
                         stub + label or power symbol on every pin, no-connect flags on unused pins
scripts/gen_pcb.py       pcbnew API: reads KiCad's own netlist export (so nets and symbol links match
                         the schematic exactly), places footprints, draws the outline and sensor slot,
                         pours GND, exports/imports Specctra for Freerouting, then removes dangling
                         autorouter leftovers and adds GND stitching vias (also one per isolated pour island)
scripts/dsn_skip_nets.py leaves GND to the pours instead of the autorouter
build.sh                 the whole flow + ERC/DRC; retries routing until the board is fully connected
export_fab.sh            Gerbers, drill, BOM, positions, STEP, schematic PDF/SVG, renders

FREEROUTING_JAR=/path/to/freerouting-2.5.0.jar ./build.sh   # regenerate everything (KiCad 10, Java 17+)
./export_fab.sh                                             # outputs only, from the routed board

The KiCad project in hardware/ opens normally in KiCad 10. The project-level library tables point at the standard ${KICAD10_SYMBOL_DIR} / ${KICAD10_FOOTPRINT_DIR} libraries.

Tools

KiCad 10 (Eeschema / Pcbnew file formats, pcbnew Python API, kicad-cli for ERC/DRC/fab outputs/3D renders), Freerouting 2.5, Python. Developed with AI-assisted pair programming (Claude Code).

License

MIT