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2 layers210 × 297 mmFra clock, the printed circuit board in 3D

A one-off gift PCB designed in KiCad 10: an ESP32 clock with a ring of 180 WS2812B‑2020 LEDs, a photo printed in exposed copper on the front, two Makerverse 8 Ω / 5 W speakers driven by two MAX98357A I²S amplifiers…

Size
210 × 297 mm
Copper layers
2
Thickness
1.6 mm
Parts
428
Nets
262
Pads
1,348
Tracks, vias
3,162, 488
Pours
3
Routed
Yes
KiCad
KiCad 10.0 (file 20260206)
Created
12 Oct 2026
Updated
12 Oct 2026

Overview

Fra clock is an open-source printed circuit board by albertoboffi-PERSONAL, from the albertoboffi-PERSONAL/fra-clock repository on GitHub. It is a 2-layer board of 210 × 297 mm with 428 parts on 262 nets, routed with 3,162 tracks and 488 vias.

It is built around the 74AHCT125D, CH340C and ESP32-WROOM-32E, with the AP2112K-3.3, USBLC6-2SC6 and WS2812B-2020 among its other parts. Its parts include 194 capacitors, 180 diodes, 20 resistors, 7 ICs and 3 transistors. It belongs with the lEDs and displays boards and the ESP32 boards of this library.

Main components

7

README

README.md

fra-clock

A one-off gift PCB designed in KiCad 10: an ESP32 clock with a ring of 180 WS2812B‑2020 LEDs, a photo printed in exposed copper on the front, two Makerverse 8 Ω / 5 W speakers driven by two MAX98357A I²S amplifiers, USB‑C power/programming (CH340C) and an NFC tag area.

Front render

Board2 layers, 210 × 297 mm (A4), R3 corners
MCUESP32‑WROOM‑32E
LEDs180 × WS2812B‑2020 (4 chains, 74AHCT125 level shifter)
Audio2 × MAX98357A → 2 × JST PH (speakers Core Electronics CE08483)
Power / USBUSB‑C (HRO TYPE‑C‑31‑M‑12), 2 A PTC, AP2112K‑3.3, USBLC6‑2SC6, CH340C
StatusRouted, DRC clean (0 errors, 0 unconnected), Gerber/drill + JLCPCB BOM/CPL generated. Not fabricated yet.

Repository layout

text
hardware/                 KiCad project – open hardware/fra_clock.kicad_pro
  fra_clock.kicad_pcb     board
  fra_clock.kicad_sch     root schematic (+ led_ring.kicad_sch sub-sheet)
  fra_clock.pretty/       project footprints (photo art ART_FOTO, speaker outline)
  3d/                     project 3D models (speaker, LCSC/EasyEDA models in lcsc/)
production/
  fra_clock_gerber_jlcpcb.zip   upload this to the fab
  gerber/                 Gerber X2 + Excellon drill (+ drill maps)
  assembly/               JLCPCB BOM and CPL (pick & place)
  preview/                Gerber renders used for the visual check
docs/
  routing-report.md       full design/routing report (Italian)
  checks/                 DRC and verification outputs referenced by the report
  images/                 3D renders
art/
  source/foto.jpeg        original photo
  generated/              dithered bitmap, rectangle list, previews
scripts/                  automation used to build the board (see scripts/README.md)

Ordering (JLCPCB)

  1. Upload production/fra_clock_gerber_jlcpcb.zip (2 layers, 1.6 mm).
  2. Surface finish: ENIG keeps the copper photo gold and flat (HASL turns it silver and uneven). Solder-mask colour sets the photo contrast.
  3. For assembly upload production/assembly/fra_clock_BOM_JLCPCB.csv and fra_clock_CPL_JLCPCB.csv, then check rotation / pin 1 in the placement preview (SOT‑23/‑5/‑6, SOIC, TQFN, WS2812B‑2020, ESP32 antenna towards the edge, USB‑C, JST, C69 polarity).
  4. Open decisions before ordering: ESP32 flash size (BOM uses N4 = C701341; N8 = C701342, N16 = C701343); stock and prices were not checked.

The NFC tag (NTAG216 sticker) has no footprint and is applied by hand in the keep-out area.

Regenerating the production files

From the repository root, with KiCad 10 (kicad-cli):

sh
KC=/Applications/KiCad/KiCad.app/Contents/MacOS/kicad-cli
$KC pcb drc --refill-zones --schematic-parity --format json --severity-all -o docs/checks/drc_latest.json hardware/fra_clock.kicad_pcb
$KC pcb export gerbers -o production/gerber/ --layers F.Cu,B.Cu,F.Paste,B.Paste,F.Silkscreen,B.Silkscreen,F.Mask,B.Mask,Edge.Cuts --subtract-soldermask --check-zones hardware/fra_clock.kicad_pcb
$KC pcb export drill -o production/gerber/ --format excellon --drill-origin absolute --excellon-units mm --excellon-zeros-format decimal --excellon-oval-format alternate --excellon-separate-th --generate-map --map-format gerberx2 hardware/fra_clock.kicad_pcb
python3 scripts/production/dump_fps.py hardware/fra_clock.kicad_pcb /tmp/fps.json
(cd production/assembly && python3 ../../scripts/production/make_bom_cpl.py /tmp/fps.json)

Known open points

See docs/routing-report.md §5: a ~1035 mm² island of the bottom GND pour around U6/C4 is tied to GND only through top-side bridges; the exposed-pad vias of U101/U102 are not plugged; the Power net class is not assigned (widths are set explicitly on the tracks).

Parts

428
QtyValueFootprintReferences
182100nFCapacitor_SMD:C_0402_1005MetricC101, C102, C201, C202, C203, C204, C205, C206, C207, C208, C209, C210, C211, C212, C213, C214 +166
180WS2812B-2020LED_SMD:LED_WS2812B-2020_PLCC4_2.0x2.0mmD201, D202, D203, D204, D205, D206, D207, D208, D209, D210, D211, D212, D213, D214, D215, D216 +164
810kResistor_SMD:R_0603_1608MetricR3, R4, R5, R6, R7, R16, R17, R18
8MountingHole_4.3mm_M4_PadMountingHole:MountingHole_4.3mm_M4_PadH3, H4, H5, H6, H9, H10, H11, H12
6MountingHole_3.2mm_M3_PadMountingHole:MountingHole_3.2mm_M3_PadH1, H2, H7, H8, H13, H14
510uFCapacitor_SMD:C_0805_2012MetricC3, C4, C6, C71, C72
4100nFCapacitor_SMD:C_0603_1608MetricC1, C5, C8, C70
4470Resistor_SMD:R_0603_1608MetricR8, R13, R14, R15
333Resistor_SMD:R_0603_1608MetricR10, R11, R12
3TestPointTestPoint:TestPoint_Pad_D1.5mmTP1, TP2, TP3
21MResistor_SMD:R_0603_1608MetricR101, R102
25.1kResistor_SMD:R_0603_1608MetricR1, R2
2CE08483fra_clock:Speaker_Makerverse_CE08483_100x45LS1, LS2
2MAX98357APackage_DFN_QFN:TQFN-16-1EP_3x3mm_P0.5mm_EP1.23x1.23mmU101, U102
2MMBT3904Package_TO_SOT_SMD:SOT-23Q1, Q2
1100kResistor_SMD:R_0603_1608MetricR9
11uFCapacitor_SMD:C_0603_1608MetricC7
122uFCapacitor_SMD:C_0805_2012MetricC2
12AFuse:Fuse_1812_4532MetricF1
12N7002Package_TO_SOT_SMD:SOT-23Q3
1470uFCapacitor_SMD:CP_Elec_8x10C69
174AHCT125Package_SO:SOIC-14_3.9x8.7mm_P1.27mmU6
1AP2112K-3.3Package_TO_SOT_SMD:SOT-23-5U1
1ART_FOTOfra_clock:ART_FOTOART1
1CH340CPackage_SO:SOIC-16_3.9x9.9mm_P1.27mmU5
1ESP32-WROOM-32ERF_Module:ESP32-WROOM-32EU3
1SPK_BOTConnector_JST:JST_PH_S2B-PH-SM4-TB_1x02-1MP_P2.00mm_HorizontalJ102
1SPK_TOPConnector_JST:JST_PH_S2B-PH-SM4-TB_1x02-1MP_P2.00mm_HorizontalJ101
1USBLC6-2SC6Package_TO_SOT_SMD:SOT-23-6U2
1USB_CConnector_USB:USB_C_Receptacle_HRO_TYPE-C-31-M-12J1

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Questions

How big is the Fra clock PCB?

It measures 210 × 297 mm and has 2 copper layers, 1.6 mm thick.

What parts does the Fra clock use?

428 parts, built around the 74AHCT125D, CH340C, ESP32-WROOM-32E and AP2112K-3.3. The full list of its parts is on this page, with links to each part's symbol and footprint where PCBKit's library has them.

Where can I download the Fra clock KiCad files?

From the albertoboffi-PERSONAL/fra-clock repository on GitHub, at the commit this page was made from: the board is hardware/fra_clock.kicad_pcb and its schematic hardware/fra_clock.kicad_sch. PCBKit opens the board in the browser, with nothing to install.

Can I use the Fra clock design in my own project?

Its repository states no licence, so its author keeps all rights: ask albertoboffi-PERSONAL before reusing the design.