T1conv

t1conv

100BASE-T1 ↔ 100BASE-TX media converter + dual CAN FD/USB adapter on one board.

Rendered from the saved hardware on 4 November 2026. Some footprints, including the USB connector, CAN chokes, and PhotoMOS relays, have no 3D model; use the assembly drawing to review their placement.

Review the design

No Gerber viewer is needed. These exports come from the KiCad sources in this repository; the PDFs and SVGs support zooming into component labels and routing.

Walkthrough

1. System: follow the Ethernet data path between the two PHYs over RGMII; the MCU configures the PHYs and provides the separate USB/CAN function.
2. Power and USB: follow USB-C VBUS through the TPS22918 soft-start switch to the AP63203 3.3 V buck; locate USB protection and the MCU USB connection.
3. Interfaces: review the T1 and RJ45 protection/filtering, then the two CAN transceivers and their switchable termination.
4. Layout: use the top assembly drawing to locate each block, then compare signal routing with the ground and power layers beneath it.
5. Bring-up: discuss PHY configuration, power/clock checks, Ethernet link testing, and CAN/USB firmware work still to complete.

Hardware

The DP83TC811 and DP83822 pass Ethernet data directly between them over RGMII. The STM32G0B1 handles PHY setup and the two CAN FD channels, each with a TCAN1042 transceiver. I'm planning to use gs_usb for CAN over USB.

Each CAN channel has switchable termination: two 60.4 Ω resistors and a PhotoMOS relay. CAN and USB share ground, so this is not an isolated adapter.

USB-C supplies power through a TPS22918 soft-start load switch and provides the USB connection. There are SWD pads and a BOOT button for programming and recovery through the STM32's ROM bootloader.

Configuration

• R18/R19 select TX clock delay on the DP83TC811 (MAC[2:0] = 101). The DP83822 also delays its incoming TX clock by default (0x17[11] = 0, 0x17[12] = 0). Each PHY handles the delay on its own input.
• Both boards boot as T1 master. One needs to be set to slave for the link to work.
• Firmware needs to advertise only 100BASE-TX full duplex on the RJ45 side. The PHY's default settings also advertise 10 Mb/s and half duplex.

Schematics

Complete schematic PDF · KiCad schematics. Click each image for a zoomable SVG.

Top level

Power

MCU

Dual CAN FD

100BASE-T1 PHY

100BASE-TX Ethernet PHY

Assembly and mechanical views

Top assembly

Board underside

Bottom assembly PDF. Both underside views are mirrored relative to the copper-layer plots below.

PCB layers

The board is four layers, ~1.6 mm thick. The planned stackup is JLC04161H-7628. All copper-layer pictures are viewed from above, including B.Cu, so features line up between layers. Click an image for its vector version.

KiCad board

Both signal layers

L1: Top copper and silkscreen

L2: Ground plane

L3: Power planes

L4: Bottom copper

Design status and export provenance

This is a design-review snapshot, not a manufacturing release. KiCad 10.0.6 checks on 4 November 2026 reported 0 unrouted connections, 4 DRC errors, and 0 ERC errors. The four DRC errors are SW1 copper-to-board-edge clearances. There are also 23 DRC warnings, 15 schematic/PCB parity warnings, and 16 ERC warnings; see the DRC report and ERC report. These checks do not establish hardware functionality or replace bring-up testing. The earlier August Gerber package predates this design and should not be used to manufacture this snapshot.

To regenerate the review exports, use KiCad 10 (including its Python pcbnew module), Inkscape, and Python 3:

python3 scripts/export-hardware.py

Use --skip-3d to update only the drawings and rule-check reports. Rendering requires the standard KiCad 3D models and the personal models referenced by ${ATJ_LIB}; missing models do not appear in the 3D views. The drawings use the symbols and footprints embedded in the design. Exported copper views refill zones in memory; the script does not save changes to the source board. Source SHA-256 hashes identify the saved hardware used for these exports.