KijaniCarrier

KijaniSpace Carrier — PCB

Start at ../../README.md: the project overview, all guides in the order to use them, and how to proceed. This file covers the board itself: generator, checks, fabrication files.

Generated for KiCad 10.0.6. Open KijaniCarrier.kicad_pcb.

What is in here

Before you open it: register the library

KiCad does not yet know where KijaniSpace.pretty lives, which is why the DRC report carries 11 library warnings. They are configuration, not design faults.

Preferences → Manage Footprint Libraries → Project Specific Libraries → add KijaniSpace.pretty from this folder, nickname KijaniSpace.

Pad order: mirrored on 2026-10-06

The first version had every module's pad row reversed. It was caught by laying a module on the table exactly as it will sit on the board — component side up, pins down — and reading the silkscreen left to right. The board now matches:

The Pololu row is the one entry not confirmed against a photo. Its pin labels are printed on the back of the module, so reading them gives the mirrored order; that is why it was flipped along with the rest. Check it the same way before soldering. VCC and GND swapped destroys the transceiver and both EZO circuits on first power-up.

Each custom footprint carries a 1 mm silkscreen label naming pin 1 — 1:VCC, 1:GND, 1:VOUT — beside the square pad. That is the marking to check the real module against.

State: fully routed, and clean once the zones are filled

With the pours filled, KiCad reports 0 unconnected, 0 electrical errors and 0 silkscreen errors. The only thing left is 11 lib_footprint_mismatch warnings: KiCad compares the board's embedded footprints against the library and the generator writes rotation differently than pcbnew would. The Gerbers come from the board, not the library, so this does not reach the fabricator. Do not run "Update Footprints from Library" — that is the one action that could act on the difference and move pads.

Seven reference designators sat on a neighbour's silkscreen, on a pad, or in the isolation slot, and the two isolator outlines ran straight across the slot; REFPOS in gen/mkpcb.py places those seven, and the isolator footprint now breaks its outline where the slot passes. One of them was less obvious than the rest: the DRC also checks a footprint's reference against its own graphics, and C1's had been sitting inside its own body circle.

253 track segments and 37 vias on 36 nets. kicad-cli on the unfilled file still shows GND as unconnected and five vias as dangling, because it does not fill zones. Fill and it goes to zero: gen/fill2.py does exactly that from KiCad's own Python, writes filled.kicad_pcb, and running the DRC on that is how the state above was measured.

What the ground plane hid

Five GND pads could not actually reach the pour, and the plane itself was in pieces. None of it is visible before the fill.

• Q2.2, R3.2 and C6.2 sat in pockets walled in by the traces around them, with half a millimetre between two keepouts as the only way out.
• U1.2, the Pololu's ground pin, is boxed in between its own two neighbours on both layers. It now leaves on the back through the gap between the V12IN and +12V runs.
• The front-layer pour below y=67 breaks into six islands. One of them carries Q4.2 and R6.2 and hung on nothing at all; another was the only copper under half the bottom edge. Each island that carries a pad now has its own stitching via.
• SWGND reached the isolators from the transceiver only through the SWGND pour, which the RS485 descents cut apart. It is a trace now.

Two pads also take the pour solid instead of through a thermal relief (gen/zonecon.py): C4.2, where three of four spokes are blocked, and U1.2, whose front-layer spokes all ran into a dead island.

gen/isl.py lists the filled islands; gen/pour.py floods the pour from one GND pad. pour.py found the first three pockets. It missed U1.2 — its raster counted a 0.44 mm squeeze beside the pad as copper, where KiCad's filler, with min_thickness and island removal, does not. The authority is the filled board, not the raster.

The pull-up resistors moved

R11 and R12 were at (60, 78) and (65, 78), where their links to the I2C bus ran up the middle of the board at x 56.5 and 57.5 and blocked the only corridor the RS485 bus could use. They now sit at (84, 50) and (84, 46), rotated 180°, directly on the SDA and SCL runs. The stubs are a few millimetres instead of forty, which suits an I2C bus better than the old position did.

The alternative was to move J8 about 8 mm west. That was rejected: J8 is a screw terminal with a cable on it, so moving it changes mechanics that were already reviewed, while two 0603 resistors change nothing but copper.

The routing discipline

Nets run in named lanes so two of them never need to cross on the same layer. Down the left edge, on the back:

The four MCU-side nets reach the isolators' top row in a fixed order, each dropping onto its own pad before continuing east to the second isolator in back-layer lanes at y 63 (SWGND), 65 (SDA) and 67 (SCL) — all north of the isolation slot at y 68.8. The RS485 pair comes down the front layer in two columns at x 67 and x 72.5, both west of the pH slot at x 74, so neither crosses a barrier.

Checks, run on every regeneration (gen/build.sh)

• barrier.py — no track and no zone crosses either isolation slot. This is the one thing the board exists for.
• check.py — endpoints on their own net's pads, pad clearance, track-to-track clearance per layer, via clearance, and the barrier again. This caught every crossing during routing; the DRC run only ever confirmed it.
• pour.py — can the filled ground actually reach every GND pad.
• endpoints.py — the narrower endpoint check, kept because it is what found the stale coordinates after the pad order was mirrored.
• kicad-cli pcb drc

Route points are written as 'REF.PAD' wherever they touch a pad, so a coordinate cannot be mistyped — an earlier pass transcribed them from a one-decimal printout and every endpoint missed its pad.

Full review before the first board

Checked, with the method, not by eye:

The netlist check is the one that matters most, because no DRC can catch a wrong net. RAIL12_EN = 5 meets J5B.1 (D5), ISO_EN = A1 meets J3.2, ONE_WIRE_PIN = A2 meets J3.1, and RS485 TX/RX meet D4/D3 the right way round — U3.2 is the module's TXD and goes to D4, which the firmware drives as its transmit pin.

Three things to check on the test board, not on the screen

1. The isolator supply is the raw cell. ISO_VIN comes off Q3's drain, whose source is +VBATT — so the isolators see 3.0 to 4.2 V, where on the bench they sit behind a 3.3 V regulator. The firmware comment says "off the cell", so this is intended, and the ADM3260 inside the isolator takes 3.0–5.5 V. But the EZO circuits hang on the isolator's output. Measure ISO1_3V9 with a full cell; it reads 3.9 V at 3.3 V in, and it must stay under the EZO's 5 V maximum.

2. The transceiver has no decoupling capacitor near it. The nearest cap on 3V3REG is C8, 25 mm away. Most MAX3485 breakout modules carry their own 100 nF — check yours. At 9600 baud on a biased bus this will work either way, but it is worth a 100 nF across the module's own VCC/GND pins in batch two.

3. The terminal blocks' bodies. The footprint is TerminalBlock_4Ucon_P3.50mm_Vertical. The pads fit any 3.5 mm terminal; the drawn body is that one part. Lay your actual terminals on the 1:1 print. The tightest spot on the board is X1 against C1, with 0.4 mm between their outlines — a deeper terminal than 8.5 mm collides there.

Mounting holes

Four M3, and not a rectangle — placement forced them apart. Measured from the board's top-left corner:

What the board says

The Value fields sit on F.Fab, which is documentation and is never printed, so before this the finished board would have carried nothing but reference designators. gen/silk.py adds 62 texts: every terminal pin by name, the cell's polarity, a plus on each electrolytic, ISOLATED on the land bridge between the two slots, PGND NEVER TO GND beside the electrodes, and a legend block in the free area right of the WaziSense connectors giving the connector functions, which control pin does what, and which parts are deliberately not fitted.

Fabrication files

out/fab/ holds everything a board house needs, and out/fab/KijaniCarrier-JLCPCB.zip is the upload: nine layers plus the two Excellon drill files, PTH and NPTH.

There used to be an out/KijaniCarrier-gerber.zip here, and it was a trap. Built on 7 October, before D1 became Q5 and before the 4-pole terminals were split, it had eleven files like the current archive and every copper layer different. It has been removed. gen/fab.sh empties out/fab/ on every run, so the file it writes is always the current one, and gen/zipcheck.py reads it back. The drill map is deliberately left out of the zip — it is a human-readable drawing with a frame around it, not a fabrication layer, and it only confuses layer detection.

The LCSC Part # and Lib columns are filled in, and both were read off JLCPCB's own stock listing on 12 October 2026 rather than guessed — a guessed part number puts the wrong component on every board. Lib says Basic or Extended, which is what decides the feeder fee. All 21 lines resolve: 11 Basic, 10 Extended, and every one of the ten is marked Economic and Standard, so no single part forces the dearer assembly tier.

The terminals are KF350-3.5 (C474892 2-pole, C474893 3-pole), not KF128. KF128 does not exist at this pitch at all; searching only for that name once produced a false "3.50 mm is not stocked", which nearly bought a complete 5.08 mm redesign of this board.

The socket rows

The board has one footprint per module, U4 to U7, but each takes two socket strips 17.78 mm apart, and an assembly line places one part per designator. The assembly files therefore name the rows U4A … U7B, with positions computed from the real pad coordinates, and those names are printed on the silkscreen beside each row so nobody has to read the CPL alone to find them.

U1 (boost) and U3 (RS485) are the same idea with one row each: the footprint is drawn as the whole plug-in module, but the assembler fits only the pin socket. Its placement point is therefore the centre of the pads, not of the footprint outline.

An early Rev C placement file had this wrong for U1. Its socket sat at Y −67.00 in the CPL instead of −72.50 — 5.5 mm above its holes — because centroid.py used the courtyard of the whole Pololu module. The assembler's placement preview showed it. gen/cplcheck.py now runs in fab.sh and fails the build if any through-hole point is more than 0.05 mm off the centre of its own holes, or any SMT point lies outside its pads. To check another set of fabrication files, pass its folder: python gen/cplcheck.py <folder>.

When JLCPCB sends the placement render, check position as well as rotation: every socket and terminal must cover its holes, and no plated hole may be left showing white.

Splitting the footprints in the board itself would have been the other way round. It was rejected on purpose: it would have moved about sixty net references, and a net swapped in that edit would have passed every check, because it would still be connected — just connected wrongly.

Only three positions stay empty

R11 and R12 (the isolators carry their own pull-ups) and U2 (JP1 does its job). Everything else is fitted; you plug in the six modules.

Rebuilding

gen/build.sh regenerates the board from scratch and ends with fillboard.py, which fills the pours with KiCad's own filler and saves in place. Without that last step the file on disk has empty pours, every GND pad reads as unconnected and the stitching vias read as dangling, none of which is true of the real board.

The generators overwrite KijaniCarrier.kicad_pcb outright, so anything edited in pcbnew is lost on the next build. They now refuse to be imported for the same reason — importing nets.py once silently appended a second set of ten zones to a board that had just been saved from KiCad.

The coordinate convention

The board sits at an offset of 20 mm from the sheet origin, and KiCad's Y axis grows downward while the placement plan's grows upward. So a part the plan puts at (64, 24) appears in KiCad at (84, 96).

What to check first

1. The four custom footprints against the real modules. Print KijaniSpace.pretty at 1:1 — kicad-cli fp export svg produces one file per footprint — and lay the parts on the paper. Pin 1 is the square pad.
2. The slot. It runs across both chains at y 82.6–85.0 in KiCad coordinates, between each isolator and its EZO circuit.
3. The pH run. U6 pin 5 (PRB) to J7: 8.1 mm, and it stays below the slot. That distance is the one constraint in this layout that is not negotiable.