A SGSS cskpin routed

Bench stimulus FeatherWing

A FeatherWing for the EPS logger stack that does four jobs:

1. Powers the whole stack from 12 V (bench supply or the car battery), so the logger needs no USB power bank.
2. Powers the Toyota steering-angle sensor (12 V, ~30 mA, switched and fused) and passes its CAN on to the Feather M4 CAN.
3. Drives the EPS signals NEP (rpm) and VSP (speed) and, with the wheels off the ground, VT3/VT6 (fake driver torque).
4. Switches IG1 for an EPS that's out of the car, on a bench.

It sits between the Adalogger and the OLED FeatherWing, on stacking headers, and every cable connector is right-angle and exits a board edge. The brief is HANDOFF.md.

Status: routed and checked in KiCad 10.0.8, nothing ordered. The board is fully routed, and the Gerbers, BOM and CPL are in fab/. Read Before ordering first: several part numbers, the relay pinout and the JLC rotations still need a human check.

KiCad 10.0.8 check (with JLCPCB's rules, bench_stim_wing.kicad_dru)	Result
ERC	0 errors. 20 warnings: symbols drawn from KiCad 7's library differ from KiCad 10's copies, and KiCad 10 renamed G6K-2
DRC	0 copper errors, 0 unconnected, 0 schematic-parity issues, including JLCPCB's 0.2 mm track-to-through-hole-pad rule and 1.0 mm / 0.15 mm text. Warnings left: stock footprint outlines touching their own pads (JLC clips those), footprints differ from KiCad 10's library copies, and J2's outline at the board edge (deliberate, edge connector)

Top (3D)	Back (3D)

Every part has a 3D model, and the models ship with the project in bench_stim_wing.3dshapes/. They're STEP files from KiCad's official library, referenced as ${KIPRJMOD}/bench_stim_wing.3dshapes/..., so the 3D viewer and STEP export work on any machine with KiCad 7 to 10, whatever 3D libraries are installed. J1 shows the Feather stacking headers' female sockets (1×16 + 1×12). Only the test pads and the JP1 solder jumper have no model, because they're bare copper.

Top layers	Back layers (seen from below)

Safety model

The user asked for this to be overbuilt. Faking VT3/VT6 makes the EPS motor steer by itself: front wheels off the ground (or the rack on a bench rig), hands clear of the wheel.

Latching DTCs. The torque-sensor and sensor-supply codes (11/15/16/17/18/67) latch until erased with the SCS procedure, so a bad VT3/VT6 fake bricks assist until you clear them. The relay swaps only VT3/VT6: the real sensor stays connected to Vcc1/Vcc2 and stays powered, so the supply checks still see a real load.

Plausibility rules (from the manual, also in EPS_PINOUT.md):

• Never send speed without rpm. At ≥ 6.2 mph with ≤ 280 rpm for 3 s, the lamp comes on with DTC 22.
• Ramp speed changes, because VSS jumps also set DTC 22.
• Don't hold ≥ 2,000 rpm at ≤ 1 mph for more than 6 minutes.

Key ON, engine off: the 12 V battery isn't being charged. The DC-DC converter doesn't charge it in that state (LiBCM FAQ), so all assist current comes from the battery. Keep bench sessions short, or put a charger on the battery.

Stack and mechanics

  OLED FeatherWing
  ─ female side of this wing's stacking headers ─
  BENCH STIM WING        top: relays, inductor, J2/J3/J4, LEDs   (tallest part: relays, 5.2 mm)
                         back: logic, test pads, J5              (back parts <= 1.25 mm, J5 4.25 mm)
  ─ long male tails into the Adalogger's female headers ─
  Adalogger FeatherWing  (CR1220 holder and microSD socket on its top: ~2-4 mm)
  Feather M4 CAN         (USB-C at the left end, CAN terminal block at the right end)
  EPS tap wing           (bottom wing, connectors facing down)

Why this slot:

• Feather ↔ Adalogger was ruled out. The Feather M4 CAN's 3.5 mm CAN terminal block (right end) and USB-C (left end) sit right where this board's back and its edge connectors would be.
• The Adalogger's top is low. The tallest parts there are the CR1220 holder (x ≈ 3–17 mm) and the microSD socket (x ≈ 27–40 mm). That's why every back-side part on this wing is ≤ 1.25 mm tall, and J5 sits at the right end, where the Adalogger is bare.
• The OLED's underside is bare, so the relays (5.2 mm), the inductor (3 mm) and the 4.25 mm GH connectors fit under it, inside the ~8.5 mm stacking-header gap.

Use Feather stacking headers (female on top, long male tails) on this wing. Check the gap with the real parts before soldering the headers.

Grounding, and running with the logger

This wing and the EPS tap wing logger run alone or together, in the car or on a bench EPS. STACK_MODES.md covers every combination: power, ground, which pins to wire, and the timers and I2C addresses they share.

The one rule: J2's ground (the stack's ground) goes to the ECU end of A4 (PG, BLK), spliced within ~10 cm of the EPS connector. On a bench, it goes to the EPS's A4 terminal. It must not go to a chassis bolt or the battery. A4 carries the 40 A motor return, so anywhere else puts an offset between the stack and the EPS's sensor ground (B9).

• Logger accuracy: that offset would shift every logger reading.
• Faked torque: it would also shift the VT3/VT6 values this board produces.

Leave J4.3 and J5.4 (GND) unwired in the car, so there's only one ground path. Fitted but unpowered (J2 unplugged), this board is passive: the relays rest on the car's wiring, and the logger keeps floating on its power bank.

Feather specification check

USB and 12 V at the same time

• Our side: the buck makes 5.05 V. After D6's drop the Feather's USB pin sees about 4.7 V.
• With a PC plugged in: the PC's 5 V is higher, so the PC carries the stack and D6 stays off. This board never back-feeds the PC.
• With 12 V gone: D6 also stops the USB cable from powering this board's 5 V rail. The relays and op-amp go dead, and so the EPS is on the car wiring.

A LiPo on the Feather. If one is plugged into the Feather's JST, its charger draws up to ~200 mA from this 5 V rail. The buck is rated 0.6 A, so that still fits, but leave the LiPo off unless you want it charging.

The current clamp's supply. The HSTS016L on the tap wing takes its 5 V from the USB pin, so on 12 V alone it gets ~4.7 V. Its output is read as Vout − Vref, which cancels most of that offset, but check its zero at key-on the first time.

Connectors

All connectors are right-angle and exit a board edge. JLC assembles the three GH connectors (J3, J4, J5: SMD, 1.25 mm pitch, awkward by hand). J2 (through-hole PH) and the Feather stacking headers are hand-soldered. The GH parts have locking latches: use JST GH housings (GHR-0xV-S) with SSHL-002T-P0.2 contacts, or buy pre-crimped GH leads.

J2, 12 V IN (top edge, JST PH S2B-PH-K, 2 mm). Pin 1 (marked +) is +12 V and pin 2 is GND. 2 A fuse.

J3, SAS / CAN (left end, JST GH 6-way). This is a pass-through: build one cable to the SAS, plus one pair from pins 5/6 to the Feather's CAN terminal.

The Feather's terminal has a 120 Ω terminator behind a solder jumper (SJ2). The SAS bus here is two nodes, so close SJ2 unless the SAS end already terminates the bus.

Second microcontroller: J3 is also the stack's port for another board. Splice its CAN-H/CAN-L into the pin 5/6 lead (no ground or power wire), keep exactly two terminators on the bus (about 60 Ω across H/L, powered off), and use IDs 0x6C0–0x6CF. See AUX_LINK.md.

J4, TORQUE (right end, top, JST GH 5-way). Break the torque sensor's VT3 and VT6 wires in a breakout harness: the CAR side goes to the sensor, the EPS side to the EPS.

J5, ECM / IG1 / ARM (right end, back, JST GH 8-way). The back silk marks "J5" with pins "1" and "8"; the pin names are below.

Loopback for free. The tap wing's J2 reads NEP (D6), VSP (D5), VT3 (A2) and VT6 (A3). Tap the EPS side of the breakout harness and the logger records exactly what the EPS receives, including whether the relay switched.

Circuit summary

Pulse output polarity. GPIO high pulls the output low (open drain), and the idle level is high. Both D4 and TX sit on independent timers: PA14 on TCC1/WO2 or TCC2/WO0, PB16 on TC6/WO0 or TCC0/WO4. Don't use TC3: the logger (eps_logger) uses it for its 1 kHz sample tick. The rates are low (NEP 1.5 pulses/rev: 22.5 Hz at 900 rpm; VSP ~1.24 Hz per mph, unverified), so plain micros() timing also works.

I2C addresses on the shared bus: RTC 0x68, OLED 0x3C, ADS1115 0x48, MCP4728 0x60, TCA9534 0x20. There are no clashes.

LEDs

Top side, in one row above the relays. Left to right: 5V, SAS, IG1, ARM, TQ, SIG, NEP, VSP; the legend is also on the back silk. The 12 V LED is in the top-left corner. TQ and SIG light when their relay is energised. NEP and VSP blink with the pulse outputs.

Test pads (back)

The pads are numbered 1–15 on the back silk; names don't fit at JLC's 1 mm minimum text height.

Design rules

Files

Rebuilding

The board was generated in a Linux cloud session. The generators ran on KiCad 7.0.11, the version Ubuntu ships. Sign-off ran on KiCad 10.0.8, which gen/setup_kicad10.sh installs from the official kicad/kicad Docker image. That image comes through Google's Docker Hub mirror, because KiCad's Launchpad PPA is blocked there and Docker Hub rate-limits anonymous pulls. The script runs KiCad 10 through chroot, which needs root. Routing used Freerouting 1.9.0 on Java 21, under xvfb-run. The files are written in KiCad 7's format. KiCad 10 opens them and asks to upgrade on save. Upgrading is fine, but then the generators would overwrite your edits, so pick one way of working.

cd gen
sh route.sh --keep-routing   # rebuild everything from the committed routing (bench_stim_wing.ses)
sh route.sh                  # full re-route with Freerouting (a different result every run)

route.sh expects kicad-cli and a Python that can import pcbnew (PY=...). A full re-route also needs the Freerouting 1.9 jar (JAR=...). On Windows with KiCad 10, point PY at KiCad's bundled python.exe, and set KICAD_SYMBOL_DIR / KICAD_FOOTPRINT_DIR if the libraries aren't found.

How it got to 0 unconnected (and JLCPCB-clean):

• Freerouting version. 2.0.1 ignored its pass limit and never finished, so routing uses 1.9.0 with -oit 100. Without that flag the post-route optimiser runs for hours.
• Rules. Signal tracks are 0.15 mm with 0.127 mm clearance, but tracks stay 0.21 mm from plated through-hole pads, per JLCPCB's 0.2 mm pad-to-trace rule. KiCad 7 doesn't export per-pad clearances to Freerouting, so make_pcb.py grows the through-hole pads in the router's copy of the board instead (dsn_router_tweaks).
• Spare DAC channels simplified. DAC C/D used to have their own op-amp stages. Routing those with the wider through-hole clearance left nets unroutable, so they now go straight to test pads 10/11.
• Hand fixes (placement.py MANUAL_ROUTES, which belongs to the committed bench_stim_wing.ses). KiCad 7 exports some back-side pads to Freerouting on the wrong layer, which leaves a few connections "connected" in its eyes but open on the board. maze_route.py (a small 4-layer grid router that keeps every clearance) and find_via.py close them:
  • Q5 gate: routed to the ARM net, 0.15 mm (gate drive only).
  • R2's +12V pad: gets a via up to the +12V track. That via is in the pad. It's fine for a 100 k pull-up, but ask JLC to plug/tent vias. To make room, an In2 +5V run moves down.
  • A NEP_DRV detour that Freerouting threaded through R27's pad gap is replaced with a direct drop.
• Net classes live in bench_stim_wing.kicad_pro, so KiCad 10 opens the board with the same rules.
• In1 (the GND plane) carries a few signal tracks. A signal-free In1 was tried, but with the wider through-hole clearances it left ~35 connections unroutable. The slots this cuts in the plane are harmless at these speeds.

check_netlist.py checks every pin in the exported netlist against design.py. When kicad10-cli is installed, route.sh also runs KiCad 10's ERC, its DRC with schematic parity, and the 3D renders.

Before ordering

1. ERC and DRC already pass in KiCad 10.0.8 (see Status). Open the board in your own KiCad 10 once anyway. If you save it there, KiCad upgrades the file and the generators would overwrite your edits.
2. Check the relay pinout against Omron's G6K datasheet: coil 1/8, COM 3/6, NC 2/7, NO 4/5. That pinout came from KiCad's G6K-2 symbol. If NC and NO are swapped, the board fails the wrong way.
3. Check stock on the LCSC numbers. Every part in the BOM now has an LCSC number, each matched to its listing in November 2026 (see JLCPCB parts). Stock moves, so re-check at upload. Use the listed alternatives if a part has run out.
4. Check every CPL rotation in JLC's preview, on both sides. The CPL already applies the community rotation corrections (see Ordering at JLCPCB), but JLC's preview is the final word. Watch especially the diodes, LEDs, SOT-23s, the relays and the GH connectors, since a polarity error there matters.
5. Check the stack gap with the real stacking headers, relays and the OLED.
6. Confirm LMR16006's FB voltage (0.765 V) against the datasheet. The output is 5.05 V with 56k/10k.

Ordering at JLCPCB

1. PCB: upload fab/bench_stim_wing_gerbers.zip. 4 layers, 1.6 mm, 50.8 × 22.86 mm; the defaults are fine (the board follows JLC's 4-layer 1 oz rules in bench_stim_wing.kicad_dru).
2. Assembly: turn on PCB Assembly, both sides (parts sit on top and back), Standard PCBA.
3. Upload fab/bench_stim_wing_bom_jlc.csv and fab/bench_stim_wing_cpl_jlc.csv. The column names match JLC's templates, so no remapping is needed.
4. Check stock and the placement preview, part by part (see Before ordering).
5. Hand-solder J1 (Feather stacking headers, Adafruit PID 2830) and J2 (JST PH S2B-PH-K) afterwards.

How the CPL is made (gen/export_fab.py), the same way Bouni's kicad-jlcpcb-tools plugin does it:

• Position: the centre of each footprint's copper pads, measured from the board's bottom-left corner (the drill/aux origin), Y up.
• Rotation: bottom-side angles are mirrored (180° − angle), then JLC's library offset is added per footprint, from the community database the plugin uses (JLCKicadTools cpl_rotations_db.csv):

Other tools: the schematic symbols carry MPN and LCSC fields, which is what the kicad-jlcpcb-tools plugin and JLC's own KiCad workflow read. Opening the project with that plugin should therefore pick up every part number. All footprints and symbols use KiCad's standard library names (Resistor_SMD:R_0402_1005Metric and so on), plus the project's own bench_stim_wing libraries for the Feather headers and JP1, through ${KIPRJMOD} library tables.

JLCPCB parts

All 38 line items have LCSC numbers in fab/bench_stim_wing_bom_jlc.csv.

About 19 Extended part types, at about $3 each in setup fees. Swapping R3 56k for a Basic value would mean recomputing the 5 V divider. Not worth it.

Firmware (next)

Nothing is written yet. A bench sketch (or a bench mode in eps_logger) needs:

• Serial commands for rpm and mph. The OLED buttons share D5/D6/D9 with the tap wing inputs, so they can't be used.
• Ramp limits and the plausibility guards: rpm ≥ ~800 whenever speed > 0, and a time limit on high rpm at zero speed.
• The expander set up as P0–P3 outputs (low), then P4/P5 read as inputs.
• Refuse to energise K1 unless ARM reads closed, and drop K1 on any serial timeout.
• Logging of what was commanded, next to what the tap wing measured.

eps_logger/config.h says D4 is the CAN boost enable. Adafruit's Feather M4 CAN schematic shows boost enable and CAN standby are internal pins PB13 and PB12, and D4 (PA14) only goes to the header. Fix that comment when the firmware is touched.