FPGA SDRAM

FPGA HDMI Development Board

A compact 4-layer FPGA development board based on the Lattice LFE5U-25F-6BG256C, designed to explore high-speed PCB design, FPGA hardware, memory interfaces, and signal integrity practices.

Project Status: Design Completed | Unfabricated | Fabrication Planned

Features

• Lattice LFE5U-25F-6BG256C FPGA
• 64 Mb SDRAM
• HDMI Output
• QSPI Flash
• USB-to-UART Programming Interface
• JTAG Header
• External Clock Oscillator
• Multi-voltage Power Distribution

PCB Specifications

PCB Stack-up

FPGA

Part Number

LFE5U-25F-6BG256C

Package

BGA-256

Core Voltage

1.1V

I/O Voltages

• 3.3V

High-Speed Interfaces

HDMI

• Controlled Differential Impedance
• Differential Pair Routing
• Length Matching
• ESD Protection
• TMDS Routing Considerations

Design Parameters

SDRAM

Memory Device

Routing Considerations

• Address Bus Routing
• Data Bus Routing
• Clock Routing
• Length Matching
• Escape Routing
• Fan-out Optimization

QSPI Flash

• High-speed SPI Routing
• Short Signal Paths
• Proper Decoupling

Power Distribution

Multiple supply rails are implemented on a single internal power layer using separated copper islands.

Power Rails

• 5 V
• 3.3 V
• 2.5 V
• 1.1 V

Design Trade-off

Using a dedicated power plane for four independent voltage rails required splitting Layer 3 into multiple power islands.

Priority was given to:

• Maintaining short current return paths
• Reducing voltage drop
• Preserving signal integrity

rather than achieving visually symmetric polygon shapes.

Placement Strategy

Component placement was driven primarily by signal integrity requirements.

Major considerations included:

• FPGA placed centrally to minimize average routing distance.
• SDRAM positioned adjacent to the FPGA to reduce memory bus length.
• HDMI connector placed close to FPGA TMDS outputs.
• USB-UART located near USB-C connector.
• Decoupling capacitors placed as close as possible to FPGA power pins.
• Clock source positioned close to FPGA clock input.
• Flash memory placed near FPGA configuration pins.

Routing Strategy

General signals

• 0.2007mm Trace Width

Power

• 0.3-0.5mm width

Fine fan-out

• 0.16mm trace width

Differential pairs

• Controlled geometry
• Constant spacing
• Constant width
• Minimal vias
• Length matched

Design Constraints

PCB Rules

Minimum Trace Width 0.1mm

Minimum Clearance 0.1mm

Minimum Via

Hole : 0.1mm

Pad : 0.25mm

FPGA Escape Routing

One of the primary design challenges was routing multiple FPGA BGA rows while maintaining clean escape paths.

Design considerations included:

• Escape routing strategy
• Via placement optimization
• Fine-pitch fan-out
• Routing density
• Layer transition management

Signal Integrity

Considerations included:

• Controlled impedance routing
• Continuous return paths
• Differential pair matching
• Minimized stubs
• Reduced via transitions
• Proper reference planes
• Clock routing optimization

Power Integrity

Design considerations

• Local decoupling
• Bulk decoupling
• Power island separation
• Current distribution
• Low impedance return paths

ESD Protection

External high-speed interfaces include ESD protection devices placed close to connectors.

Protected Interfaces

• HDMI
• USB

Design Challenges

Some of the major challenges during this project included:

• Routing HDMI differential pairs while maintaining impedance.
• FPGA BGA escape routing.
• Routing the SDRAM memory interface.
• Creating four separate power islands on a single power layer.
• Maintaining signal integrity within a compact layout.
• Optimizing placement without sacrificing routing quality.

Future Improvements

• PCB fabrication
• Assembly
• Bring-up
• FPGA programming
• SDRAM validation
• HDMI output testing
• Signal integrity measurements
• Power integrity measurements
• Revision B improvements

Repository Contents

PCB/
│── FPGA_SDRAM.kicad_pcb
│── FPGA_SDRAM.kicad_pro

Gerbers/
│── gerbers.zip
│── gerbers/

Schematics/
│── FPGA_SDRAM.kicad_sch

Images/
│── 3D_Model/
│── PCB_Images/

README.md

License

MIT License

Acknowledgements

This project was completed as a personal learning project to gain practical experience in FPGA hardware design, high-speed PCB layout, signal integrity, and power integrity.

"Designed during sophomore year as a self-directed learning project. First BGA package, first 4-layer board, first FPGA design."

Feedback and suggestions are always welcome