CHIPDOWNARM

flowchart TD
    subgraph PowerDomain["⚡ Power Architecture (1.8V - 6.5V)"]
        VIN["DC Power In (J1) / Li-SOCl2 / Li-Po"] --> F1["Polyfuse PTC (F1)"]
        F1 --> D1["TVS Diode Protection"]
        D1 --> U2["TI TPS62840 Buck (60nA Iq)"]
        U2 --> L1["1.5µH Shielded Inductor"]
        L1 --> VCC3["+3V0 System Rail"]
        VCC3 --> FB1["Ferrite Bead (FB1)"]
        FB1 --> VDDA["Filtered Analog Power (VDDA)"]
    end

    subgraph CoreDomain["🧠 Compute and RF Engine"]
        U1["STM32WLE5CCU6 (ARM Cortex-M4 @ 48MHz)"]
        Y1["32.000 MHz TCXO (Y1)"] -->|"RF Master Clock"| U1
        Y2["32.768 kHz RTC Crystal (Y2)"] -->|"Low Power RTC"| U1
        VCC3 --> U1
        VDDA --> U1
    end

    subgraph RFDomain["📡 Sub-GHz RF Frontend (150-960 MHz)"]
        U1 -->|"RF_PA_OUT"| RFFilt["LC Harmonics Filter & Matching Network"]
        RFFilt -->|"50Ω Coplanar Microstrip"| J2["SMA Edge-Mount Connector (J2)"]
    end

flowchart LR
    BATT["Battery / External Input<br/><b>1.8V - 6.5V</b>"] -->|F1: PTC Fuse| REG["TPS62840<br/><b>Buck Regulator</b><br/>Iq = 60 nA | Eff = 92%"]
    REG -->|VOUT = 3.0V| RAIL["+3V0 System Rail<br/>(Inner Layer 2 Plane)"]
    
    RAIL -->|"100nF + 4.7µF"| MCU["STM32WLE5 Core<br/>Sleep: 1.1 µA<br/>TX (+22dBm): 118 mA"]
    RAIL -->|"100nF"| SENS["SHTC3 Sensor<br/>Active: 800 µA<br/>Sleep: 0.2 µA"]
    RAIL -->|"100nF + TCXO Reg"| TCXO["32 MHz TCXO<br/>Warmup: 2 ms"]
    RAIL -->|FB1: Ferrite Filter| RF_ANA["RF & VDDA Power<br/>Multi-stage decoupling"]

========================================================================================
Layer 1 (Top / F.Cu): Component SMD Pads, 50Ω RF Coplanar Microstrips, Buck Power Loop
---------------------------------- Dielectric Prepreg (0.21mm, FR-4, Er=4.5) -----------
Layer 2 (Inner 1 / In1.Cu): Solid Continuous Ground Plane (GND) - Zero Slots
---------------------------------- Core Dielectric (1.065mm, FR-4, Er=4.5) -------------
Layer 3 (Inner 2 / In2.Cu): Dedicated +3V0 Power Plane & RF Return Shield
---------------------------------- Dielectric Prepreg (0.21mm, FR-4, Er=4.5) -----------
Layer 4 (Bottom / B.Cu): Digital Control Signals & Secondary Ground Shield
========================================================================================

CHIPDOWNARM/
├── CHIPDOWNARM.kicad_pcb        # KiCad 8/9 PCB Layout File (4-Layer, 0 DRC Errors)
├── CHIPDOWNARM.kicad_sch        # KiCad Schematic File
├── CHIPDOWNARM.kicad_pro        # KiCad Project Definitions
├── CHIPDOWNARM_Schematic.pdf    # Complete vector schematic PDF
├── CHIPDOWNARM.step             # High-precision 3D mechanical model (STEP AP214)
├── CHIPDOWNARM_BOM.xml          # Sourcing Bill of Materials
├── gerbers/                     # Standard RS-274X Fabrication Gerbers & Excellon Drills
│   ├── CHIPDOWNARM-F_Cu.gtl     # Top Copper Layer
│   ├── CHIPDOWNARM-In1_Cu.g1    # Layer 2 Ground Plane
│   ├── CHIPDOWNARM-In2_Cu.g2    # Layer 3 Power Plane
│   ├── CHIPDOWNARM-B_Cu.gbl     # Bottom Copper Layer
│   ├── CHIPDOWNARM.drl          # NC Drill file
│   └── ...                      # Masks, silkscreens, edge cuts
├── docs/
│   └── img/                     # 3D Photorealistic raytracing renders & SVG layer previews
│       ├── render_isometric_top.png
│       ├── render_isometric_bottom.png
│       ├── render_top.png
│       └── layer_l*.svg
├── .gitignore                   # Clean Git configuration for EDA projects
└── README.md                    # Comprehensive hardware documentation