Carrier

Carrier electrical and placement study

Revision A adds editable KiCad 10 carrier and manual-fixture schematics, exact part selections, an unrouted carrier, and reproducible checks. The WROOM, LCD, six control centres and existing enclosure geometry are preserved. This completes the authorized electrical study; physical acceptance and fabrication release remain open.

Open the preview for placement views and schematic SVGs. Open carrier.kicad_pro or fixture.kicad_pro in KiCad to edit the native circuits. The fixture has a reference schematic only, with no fixture PCB or probe mechanics.

Files and reproduction

From the repository root:

python3 hardware/electronics/build.py

The checked tools are KiCad 10.0.6 and FreeCAD 1.1.4. KiCad's Python needs pcbnew and wx; FreeCAD's Python needs FreeCAD and Part. The generator otherwise uses the Python standard library. Defaults point to installed macOS applications. For another installation, set SPECCY_KICAD_SHARE, SPECCY_KICAD_PYTHON and SPECCY_FREECAD_PYTHON; make kicad-cli available and install its standard 3D models. No manufacturer documents are downloaded by the build.

Rebuilding replaces native files and generated reports. Preserve repeatable changes in design.py or the generator; direct KiCad edits remain valid for review but are overwritten on rebuild. python3 hardware/electronics/check.py checks existing netlists/BOMs/reports without generating them. Native board and STEP checks run as part of the full build.

The build checks both circuits with every ERC rule enabled and no exclusions. It checks exact pins/NCs/MPNs, firmware GPIOs, BOM parity and three deliberately incorrect netlists. It reopens the board, checks pad nets, original outline, sides, thickness and pogo access, then reopens both STEP exports. DRC is saved in full: one shell-stake/courtyard conflict, 70 unconnected items, zero schematic parity issues. The checker requires that exact known conflict and rejects additional placement violations. Its successful exit means the study is reproduced and its gate is visible; it does not mean DRC or physical acceptance passed.

Serve the preview locally if needed:

python3 -m http.server 8790 --bind 127.0.0.1

Open http://127.0.0.1:8790/hardware/electronics/previews/. Safari inspection confirmed that all four SVG previews load.

Carrier power and reset

J1 is GCT USB3076-30-A, Micro-B power only. D+/D−/ID are explicitly unconnected; the shell is grounded. Use a regulated, rated dedicated power source of at least 1 A. The circuit does not enumerate or negotiate USB host current. F1 is Bourns MF-PSMF075X-2, a 0.75 A resettable fuse, followed by an ESD shunt and TI TLV75733PDBVR. The LDO input and enable share VBUS_FUSED; output is 3.3 V. C1/C2 are 10 µF, 10 V X5R; C3 is a local 100 nF bypass at the module supply.

D1 CDSOD323-T05C has 5.0 V working peak, 6.0 V minimum breakdown and 9.8 V maximum clamp at 1 A. It does not protect the LDO's 5.5 V recommended / 6 V absolute input limit against sustained overvoltage. Limit the prototype source to 4.75–5.00 V at the TVS; reselect or qualify protection before using a wider input range. The 5.25 V sweep in the power report is a thermal boundary case outside this TVS rating. No system ESD result is claimed.

R1/C4 give EN a 10 kΩ pull-up and 1 µF capacitor. R2 pulls GPIO0/BOOT high; R3 and R4 hold GPIO2 and GPIO12 low. The latter preserves the module's 3.3 V flash selection. Other unused and flash-connected pins have explicit NC markers. Module ground pins 1/15/38/39 are on GND. The module footprint retains its ground-pad array with provisional 0.30 mm drills; its antenna keepout stays in DRC. Radios remain disabled.

LCD and controls

J2 is a carrier wire-pad array, not a purchased connector. Its order matches the manufacturer's module schematic:

Waveshare 26117 remains the selected GC9107 128 × 128 module. The manufacturer circuit has a backlight transistor; BL drives its base through 1 kΩ rather than supplying LED current directly. The module also includes its own regulator. Supply it with the specified 3.3 V. Its FAQ states up to 60 mA. Confirm the purchased revision's physical pad order after MX1.25 removal; source connector numbering alone does not prove solder-pad orientation.

SW1–SW6 are TE 2337228-2, also named USLPT3026EL2TR: Up 26, Down 27, Left 32, Right 33, Fire 13, Menu 14. Each is active low to GND, using firmware pull-ups and 10 ms debounce. On the TE drawing, T1/T2 share one contact and T3/T4 share the other. The footprint numbers each pair 1 and 2 and keeps the central 1.60 × 2.60 mm free of pads, tracks, vias and fills.

Programming contacts and fixture

Both placement views put USB at the bottom. In the underside view, pad 1 is leftmost. In the front projection, pad 1 is at CAD X = 15.75 and the numbering runs toward decreasing X. Do not copy the old generic CAD label's order. A probe carrier viewed from its contact tips must mirror the underside view; wire by number and continuity-test the mating pair.

J3 pad centres are 1.50 mm apart at CAD Y = 8.25. This is 0.20 mm forward of the old generic pads and stays within the unchanged opening. Pads are 1.05 × 1.50 mm with no paste. Exact probes, contact force, alignment and mating sequence remain a physical gate.

The handheld receives power through Micro-B. Fixture J2 pin 1 (adapter VCC) is NC. Its other pins are logical GND/TX/RX, not a universal adapter cable pinout. Fixture J3 accepts its own regulated 3.3 V ±5% rail with common ground. That rail powers the fixture circuitry only and has no connection to device pad 2. A controller's regulated rail or a separate regulated bench source can supply it; do not obtain it from the handheld sense pad. Use a 3.3 V logic UART adapter.

TI SN74LVC2G125DCUR buffers both UART directions. Both active-low enables have a pull-up and share the open-drain output of TLV7041DBVR. A 523 kΩ / 1 MΩ divider senses the handheld; LM4040A20IDBZR supplies a 2.048 V reference. External feedback adds hysteresis to the comparator's internal hysteresis. The nominal enable/disable points are about 3.14 / 3.08 V; the analysis records assumptions and variation. Sense-divider current is about 2.17 µA at 3.3 V. The comparator inputs tolerate 7 V while unpowered; the buffer has Ioff protection. R8/R9 define buffer input levels when an adapter or device is absent.

With the device rail absent, the enable pull-up keeps both buffer outputs high impedance. Manual BOOT/RESET only sink to GND. Confirm actual output levels, leakage and ramp/brownout behavior on hardware; static topology and datasheet limits do not prove every transient sequence.

Manual sequence after circuit/continuity review:

1. With device USB off, mate the numbered contacts and connect common ground, the local fixture rail and UART. Confirm device pad 2 is not driven.
2. Apply qualified Micro-B power. Hold BOOT, pulse RESET low for at least 10 ms, release RESET, then start esptool. Keep BOOT low through reset and the manufacturer's 1 ms strap-hold interval.
3. Use esptool's --before no_reset --after no_reset settings; DTR/RTS have no circuit here. Use the built mode's bootloader at 0x1000, partitions at 0x8000 and app at 0x10000, as described in the firmware guide.
4. Release BOOT after esptool connects. After a complete flash, pulse RESET with BOOT released to run. Interrupted programming or invalid content uses the same manual bootloader entry and full reflash.

Required bench cases remain: cold boot; BOOT/RESET and normal flash; USB present/absent with fixture and adapter powered/unpowered; disconnected contacts; brownout; interrupted flash; invalid-content recovery; complete return to execution. Record device 3V3, both UART directions, EN/BOOT and off-state currents.

Fit and thermal gates

The carrier follows the native CarrierPCB outline, including corner reliefs and the antenna cutout. Nominal blank size stays 20.8 × 34.8 × 0.8 mm; the cut/rounded native solid's Y extent is 34.769694 mm. KiCad's board-only STEP exports a 0.71 mm dielectric core; copper/mask layers complete the nominal 0.8 mm stack. The report aligns the core within CAD Z = 4.8–5.6. Its 0.5 mm grid containment check supplements the exact native-board outline check; it is not a tolerance certification. Selected package envelopes show no intersection with the unchanged case/LCD solids in the checked nominal model.

If the selected LDO cannot meet thermal limits, return that result for an explicit power-strategy decision. Do not treat its 1 A electrical rating, thermal shutdown or a nominal box fit as continuous-load acceptance. No enclosure, legacy CAD exports, firmware, game content, routed PCB or fabrication package is changed by this phase.

Sources and document hashes are in sources.json, with the cross-project references in research. Full manufacturer PDFs remain outside the repository.