ShutterClock

ShutterClock PCB

• v1.2 (2026-10-21, not ordered): v1.1 + battery-backed RTC. Board grown to 100 x 100 mm (mounting holes 93 x 93 mm); a 12 mm strip at the bottom carries U5 Akizuki AE-RX8900 (RX8900CE DTCXO RTC, I2C 0x32 on the XIAO D4 = SDA / D5 = SCL, VDD from 3V3_SYS, FOE tied to GND so FOUT stays off), BT1 CH243-2032LF vertical CR2032 holder and D7 1N4148 in series with the cell (the RX8900 has an internal VDD -> VBAT charge path; a CR2032 must not be charged). SW1 and ZD1 moved 1-2 mm right to make room for the I2C / 3V3 tracks along the left edge. DRC 0 errors / 0 unconnected. ShutterClock_v1.2_gerbers.zip, render_top.png, ../docs/assembly/placement_top_v1.2.png. Open before ordering: the holder's centre pin is assumed to be "+" (drawing CH243-0308 does not mark polarity) - check with a cell and a meter on the real part; if the outer pins are "+", swap BT1 pad nets in generate_board.py.

• v1.1 (2026-10-21, not ordered): the three v1.0 errata fixed (C1 polarity nets, U2 hole pattern 40 x 17.5 mm, F1 clip pins along the fuse axis at 7.0 mm; ZD1 moved 3.5 mm down to make room). DRC 0 errors / 0 unconnected (40 silk warnings). Gerbers ShutterClock_v1.1_gerbers.zip, renders render_top.png / render_bottom.png, placement map ../docs/assembly/placement_top_v1.1.png. Same outline, mounting holes and connector positions as v1.0, so the v1.0 bench results apply.

• v1.0 (ordered 2026-10-08, JLCPCB W2026100808086019 / Y14-13437881A, 5 pcs; board #1 assembled and bench-tested 2026-10-20): ShutterClock_v1.0_gerbers.zip, render_top_v1.0.png / render_bottom_v1.0.png. Build the remaining v1.0 boards with the workarounds in ../docs/02_assembly.md.

• Board: 100 x 88 mm, 2-layer. Bottom layer is a GND pour; most signals on top, the VIN trunk and a few long signals on the bottom.

• Mounting: 4x M3 (3.2 mm) holes, centres 3.5 mm from each edge (93 x 81 mm spacing).

• Generated by generate_board.py (+ tracks.py) → ShutterClock.kicad_pcb (KiCad 10). Never hand-edit the .kicad_pcb. Run: /Applications/KiCad/KiCad.app/Contents/Frameworks/Python.framework/Versions/Current/bin/python3 generate_board.py then kicad-cli pcb drc --severity-error --severity-warning --format json --output drc.json ShutterClock.kicad_pcb and python3 drc_report.py. Current state: DRC 0 errors, 0 unconnected (46 warnings: silkscreen overlaps, library-name notes).

• Gerbers for JLCPCB (2 layers, 1.6 mm, HASL, defaults): see the version list above. Export: kicad-cli pcb export gerbers --layers F.Cu,B.Cu,F.Paste,B.Paste,F.Silkscreen,B.Silkscreen,F.Mask,B.Mask,Edge_Cuts --subtract-soldermask, kicad-cli pcb export drill --format excellon --excellon-units mm --generate-map --map-format gerberx2, zip the folder. kicad-cli = /Applications/KiCad/KiCad.app/Contents/MacOS/kicad-cli.

• Circuit: spec v0.11 §6 (independent review applied). BOM: ../docs/01_parts.md. Assembly guide: ../docs/02_assembly.md (placement map generated by ../docs/assembly/draw_placement.py).

Errata v1.0 (fixed in v1.1)

1. C1 silkscreen "+" is on the wrong pad. generate_board.py assigns C1 pad 1 (the square pad, which the KiCad CP_Radial footprint marks "+") to GND and pad 2 to VIN. Electrically the board is fine; mount C1 with its + lead in the right-hand (round) pad. v1.1: swap the nets to {"1": "VIN", "2": "GND"} and re-route the two C1 tracks. C3 is correct (pad 1 = CAM_P).
2. U2 (MBC2596-01) hole pattern is 40.0 x 17.5 mm (measured on the real module 2026-10-19), not the 38 x 16 mm placeholder (±19.0 / ±8.0). v1.0 boards: the module is connected with bent tinned wire. v1.1: fp_buck() pads at ±20.0 / ±8.75 mm.
3. F1 fuse clips (FUC-03A): the two pins of one clip lie ALONG the fuse axis, not across it as in fp_fuseclips() (pairs 6.7 mm apart across the axis). v1.0 boards: cut one pin per clip and solder the other into one hole (keep the outer pin on one clip and the inner pin on the other so the clip spacing stays 18 mm), or put an inline fuse holder in the battery + lead and bridge the F1 holes. v1.1: rotate the footprint; pin pitch along the axis still to be measured.

Open items (ordered before bench verification — check these when the boards arrive)

1. U2 hole positions → wrong, see Errata 2.
2. Bench-verify the circuit on the breadboard first (spec §6.5): LM2596 + 4700 µF with the D7500 (and D7200), keep-alive follower voltage, shot detection on A1.
3. Independent layout review (as for SnowGauge v1.2) — not done yet.
4. XIAO SMD-pad clearance to the KA_EN / CAM_EN tracks is at the 0.2 mm minimum; fine for JLCPCB but do not tighten.

Firmware pin map (single source of truth for the board)

Rules: never drive CAM_EN and KA_EN so that the camera is released on the keep-alive path; enter keep-alive only from CAM_EN = on; drop to CAM_EN = on if A1 shows > 50 mA during keep-alive; low-battery cutoff 11.5 V.

Connectors and jumpers

• J1 (5.08 mm screw terminal, bottom-left): battery + / − (12 V lead-acid / LiFePO4; fuse F1 5 A, Q1 reverse protection, 2x P4KE15A TVS)
• J2 (5.08 mm screw terminal, bottom-right): camera + / − → Nikon EP-5B cable. The − side is the sense shunt — keep it as the only camera ground.
• J3 (3.5 mm stereo jack, right edge): tip = SHUTTER, ring = AF, sleeve = common → off-the-shelf 3.5 mm → MC-DC2 / 10-pin release cables (verify the cable's pinout with a meter)
• JP1 (near the XIAO): shunt fitted normally; remove before connecting USB to the XIAO (same rule as SnowGauge)
• JP2 (below Q3): shunt fitted = camera supply always on (bypasses Q3)
• U2: 4-pin module socket positions; set the trimpot to 9.4 V and remove the module's LED before fitting

Silkscreen notes

"REMOVE JP1 BEFORE USB", "U2: SET 9.4V, REMOVE LED", "JP2=ALWAYS ON", battery and camera polarity, diode cathodes marked "K".