PCM1802DB

Texas Instruments

-40℃~+85℃ 2 24 3.3V、5V 96000Hz Audio Analog-to-Digital Converter Built-in I2S SSOP-20 ADCs/DACs - Special Purpose ROHS

Extended

Category: ADCs, DACs Special Purpose
Package: SSOP-20
Pins: 20

Overview

The PCM1802DB is an ADCs, DACs Special Purpose made by Texas Instruments in a SSOP-20 package with 20 pins. -40℃~+85℃ 2 24 3.3V、5V 96000Hz Audio Analog-to-Digital Converter Built-in I2S SSOP-20 ADCs/DACs - Special Purpose ROHS.

PCBKit's library has its KiCad symbol (EasyEDA_Cloud:PCM1802DBR, from EasyEDA) and its footprint (Package_SO:SSOP-20_5.3x7.2mm_P0.65mm, from KiCad's library), ready for a KiCad board. 129 are in stock at JLCPCB (part C2866894). 5 open-source boards in 4 repositories on GitHub use it.

Symbol

EasyEDA_Cloud:PCM1802DBRFrom EasyEDA

Footprint

Package_SO:SSOP-20_5.3x7.2mm_P0.65mmFrom KiCad's library

From the datasheet

Supply, least: 4.5 V · VCC, recommended operating min · p. 6
Supply, most: 5.5 V · VCC, recommended operating max · p. 6
Supply, least: 2.7 V · VDD, recommended operating min · p. 6
Supply, most: 3.6 V · VDD, recommended operating max · p. 6
Supply, absolute maximum: 6.5 V · VCC, absolute max · p. 4
Supply, absolute maximum: 4 V · VDD, absolute max · p. 4
Works from: -40 °C · Operating free-air temperature min · p. 4
Works up to: 85 °C · Operating free-air temperature max · p. 4
Junction, hottest: 150 °C · Junction temperature absolute max · p. 4
Takes working: 32.3 mA · sum of ICC and IDD, typical at 44.1 kHz, VCC = 5 V, VDD = 3.3 V · p. 6
Takes at most: 40 mA · sum of ICC and IDD, max at 44.1 kHz, VCC = 5 V, VDD = 3.3 V · p. 6
Junction to air (DB (SSOP)): 80.8 K/W · Junction-to-ambient thermal resistance · p. 5
Junction to case (DB (SSOP)): 40 K/W · Junction-to-case top thermal resistance · p. 5
Junction to board (DB (SSOP)): 37.6 K/W · Junction-to-board thermal resistance · p. 5

What it is and has

ADC: 24-bit delta-sigma stereo · p. 1
Analog input: Single-ended, 3 VP–P · p. 1
Antialiasing filter: Included · p. 1
Oversampling: ×64, ×128 · p. 1
Pass-band ripple: ±0.05 dB · p. 1
Stop-band attenuation: –65 dB · p. 1
High-pass filter: On-chip, 0.84 Hz at 44.1 kHz · p. 1
THD+N: 96 dB typical · p. 1
SNR: 105 dB typical · p. 1
Dynamic range: 105 dB typical · p. 1
PCM audio interface: Selectable master and slave modes · p. 1
Sampling rate: 16 kHz to 96 kHz · p. 1
System clock: 256 fS, 384 fS, 512 fS, 768 fS · p. 1
Power supplies: 5 V analog, 3.3 V digital · p. 1
Package: 20-pin SSOP · p. 1

Around it

cap 1 µF: between L-Ch IN and VINL; C1, AC coupling; approximately 8-Hz input HPF cutoff. · p. 22
cap 0.1 µF: between VCC and AGND; Ceramic bypass capacitor, as close to the pins as possible. · p. 24
cap 10 µF: between VCC and AGND; Tantalum bypass capacitor, as close to the pins as possible. · p. 24
cap 0.1 µF: between VREF1 and AGND; Ceramic; place as close as possible to VREF1. · p. 24
cap 10 µF: between VREF1 and AGND; Electrolytic; place as close as possible to VREF1. · p. 24
cap 0.1 µF: between VREF2 and AGND; Ceramic; recommended for a noisy analog supply, close to VREF2. · p. 24
cap 10 µF: between VREF2 and AGND; Electrolytic; recommended for a noisy analog supply, close to VREF2. · p. 24
res 1 kΩ: between VCC and VREF2; Use with a noisy analog supply; not required for a clean supply. · p. 24

Specifications

Parameter	Conditions	As printed	Page
Supply voltage VCC		max 6.5 V	4
Supply voltage VDD		max 4 V	4
Ground voltage differences	AGND and DGND; maximum magnitude ±0.1 V	max 0.1 V	4
Supply voltage difference (VCC – VDD)	VCC and VDD	max 3 V	4
Digital input voltage	FSYNC, LRCK, BCK, and DOUT; maximum VDD + 0.3 V	min -0.3 V	4
Digital input voltage	PDWN, BYPAS, SCKI, OSR, FMT0, FMT1, MODE0, and MODE1	min -0.3 · max 6.5 V	4
Analog input voltage	VINL, VINR, VREF1, and VREF2; maximum VCC + 0.3 V	min -0.3 V	4
Input current (any pins except supplies)	Maximum magnitude ±10 mA	max 10 mA	4
Ambient temperature under bias		min -40 · max 125 °C	4
Junction temperature		max 150 °C	4
Package temperature (IR reflow, peak)		max 260 °C	4
Storage temperature, Tstg Tstg		min -55 · max 150 °C	4
Electrostatic discharge V(ESD)	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001; rated magnitude ±1500 V	max 1500 V	4
Electrostatic discharge V(ESD)	Charged-device model (CDM), per JEDEC specification JESD22-C101; rated magnitude ±1000 V	max 1000 V	4
Analog supply voltage, VCC VCC	Nominal value	typ 5 V	4
Digital supply voltage, VDD VDD	Nominal value	typ 3.3 V	4
Analog input voltage, full-scale (–0 dB)	Nominal value	typ 3 VP–P	4
Digital input clock frequency	Sampling clock, as labeled in this table	min 8.192 · max 49.152 MHz	4
Digital input clock frequency	System clock, as labeled in this table	min 32 · max 96 kHz	4
Digital output load capacitance		max 20 pF	4
Operating free-air temperature, TA TA		min -40 · max 85 °C	4
Junction-to-ambient thermal resistance RθJA	DB (SSOP), 20 pins	typ 80.8 °C/W	5
Junction-to-case (top) thermal resistance RθJC(top)	DB (SSOP), 20 pins	typ 40 °C/W	5
Junction-to-board thermal resistance RθJB	DB (SSOP), 20 pins	typ 37.6 °C/W	5
Junction-to-top characterization parameter ψJT	DB (SSOP), 20 pins	typ 7.2 °C/W	5
Junction-to-board characterization parameter ψJB	DB (SSOP), 20 pins	typ 37 °C/W	5
Resolution		typ 24 Bits	5
Sampling frequency fS		min 16 · typ 44.1 · max 96 kHz	5
System clock frequency	256 fS	min 4.096 · typ 11.2896 · max 24.576 MHz	5
System clock frequency	384 fS	min 6.144 · typ 16.9344 · max 36.864 MHz	5
System clock frequency	512 fS	min 8.192 · typ 22.5792 · max 49.152 MHz	5
System clock frequency	768 fS; maximum not applicable at fS = 96 kHz	min 12.288 · typ 33.8688 MHz	5
Input logic level VIH	FSYNC, LRCK, BCK; maximum VDD	min 2 VDC	5
Input logic level VIL	FSYNC, LRCK, BCK	min 0 · max 0.8 VDC	5
Input logic level VIH	PDWN, BYPAS, SCKI, OSR, FMT0, FMT1, MODE0, MODE1	min 2 · max 5.5 VDC	5
Input logic level VIL	PDWN, BYPAS, SCKI, OSR, FMT0, FMT1, MODE0, MODE1	min 0 · max 0.8 VDC	5
Input logic current IIH	VIN = VDD; FSYNC, LRCK, BCK, SCKI; maximum magnitude ±10 uA	max 10 uA	5
Input logic current IIL	VIN = 0 V; FSYNC, LRCK, BCK, SCKI; maximum magnitude ±10 uA	max 10 uA	5
Input logic current IIH	VIN = VDD; PDWN, BYPAS, OSR, FMT0, FMT1, MODE0, MODE1	typ 65 · max 100 uA	5
Input logic current IIL	VIN = 0 V; PDWN, BYPAS, OSR, FMT0, FMT1, MODE0, MODE1; maximum magnitude ±10 uA	max 10 uA	5
Output logic level VOH	IOUT = –1 mA; FSYNC, LRCK, BCK in master mode, DOUT	min 2.8 VDC	5
Output logic level VOL	IOUT = 1 mA; FSYNC, LRCK, BCK in master mode, DOUT	max 0.5 VDC	5
Gain mismatch, channel-to-channel	Typical ±1%, maximum ±4% of FSR	typ 1 · max 4 FSR	5
Gain error	Typical ±2%, maximum ±6% of FSR	typ 2 · max 6 FSR	5
Bipolar zero error	HPF bypassed; typical ±2% of FSR	typ 2 FSR	5
Total harmonic distortion + noise THD+N	fS = 44.1 kHz, VIN = –0.5 dB	typ 0.0015 · max 0.003 %	6
Total harmonic distortion + noise THD+N	fS = 96 kHz, VIN = –0.5 dB, system clock = 256 fS, oversampling ratio = ×64	typ 0.0025 %	6
Total harmonic distortion + noise THD+N	fS = 44.1 kHz, VIN = –60 dB	typ 0.7 %	6
Total harmonic distortion + noise THD+N	fS = 96 kHz, VIN = –60 dB, system clock = 256 fS, oversampling ratio = ×64	typ 1.2 %	6
Dynamic range	fS = 44.1 kHz, A-weighted	min 100 · typ 105 dB	6
Dynamic range	fS = 96 kHz, A-weighted, system clock = 256 fS, oversampling ratio = ×64	typ 103 dB	6
Signal to noise ratio	fS = 44.1 kHz, A-weighted	min 100 · typ 105 dB	6
Signal to noise ratio	fS = 96 kHz, A-weighted, system clock = 256 fS, oversampling ratio = ×64	typ 103 dB	6
Channel separation	fS = 44.1 kHz	min 96 · typ 103 dB	6
Channel separation	fS = 96 kHz, system clock = 256 fS, oversampling ratio = ×64	typ 98 dB	6
Input impedance		typ 20 kΩ	6
Antialiasing filter frequency response	–3 dB	typ 300 kHz	6
Pass-band ripple	Maximum magnitude ±0.05 dB	max 0.05 dB	6
Stop-band attenuation		min -65 dB	6
Voltage VCC		min 4.5 · typ 5 · max 5.5 VDC	6
Voltage VDD		min 2.7 · typ 3.3 · max 3.6 VDC	6
Supply current ICC	VCC = 5 V, VDD = 3.3 V; minimum load on DOUT, BCK, LRCK, FSYNC	typ 24 · max 30 mA	6
Supply current IDD	fS = 44.1 kHz, VCC = 5 V, VDD = 3.3 V; minimum load on DOUT, BCK, LRCK, FSYNC	typ 8.3 · max 10 mA	6
Supply current IDD	fS = 96 kHz, VCC = 5 V, VDD = 3.3 V; minimum load on DOUT, BCK, LRCK, FSYNC	typ 17 mA	6
Power dissipation PD	Operation; fS = 44.1 kHz, VCC = 5 V, VDD = 3.3 V	typ 147 · max 183 mW	6
Power dissipation PD	Operation; fS = 96 kHz, VCC = 5 V, VDD = 3.3 V	typ 176 mW	6
Power dissipation PD	Power down; VCC = 5 V, VDD = 3.3 V	typ 0.5 mW	6

Pins, by the datasheet

1 VINL: Analog input, L-channel. · p. 3
2 VINR: Analog input, R-channel. · p. 3
3 VREF1: Reference-1 decoupling capacitor. · p. 3
4 VREF2: Reference-2 voltage input, normally connected to VCC. · p. 3
5 VCC: Analog power supply, 5 V. · p. 3
6 AGND: Analog GND. · p. 3
7 PDWN: Active-low power-down control; Schmitt-trigger input with internal pulldown, 5-V tolerant. · p. 3
8 BYPAS: HPF bypass control: low selects normal DC-cut mode; high selects bypass mode. · p. 3
9 FSYNC: Frame synchronous clock input and output; Schmitt-trigger input. · p. 3
10 LRCK: Sampling clock input and output; Schmitt-trigger input. · p. 3
11 BCK: Bit clock input and output; Schmitt-trigger input. · p. 3
12 DOUT: Audio data output. · p. 3
13 DGND: Digital GND. · p. 3
14 VDD: Digital power supply, 3.3 V. · p. 3
15 SCKI: System clock input: 256 fS, 384 fS, 512 fS, or 768 fS; Schmitt-trigger input, 5-V tolerant. · p. 3
16 OSR: Oversampling ratio select: low selects ×64 fS; high selects ×128 fS. · p. 3
17 FMT0: Audio data format select 0. · p. 3
18 FMT1: Audio data format select 1. · p. 3
19 MODE0: Mode select 0. · p. 3
20 MODE1: Mode select 1. · p. 3

Ordering codes, by the datasheet

PCM1802DB: SSOP (DB), 20 pins · 65 per tube; lead finish Call TI | Nipdau; -40 to 85 °C. · p. 27
PCM1802DB.B: SSOP (DB), 20 pins · 65 per tube; lead finish Call TI; -40 to 85 °C. · p. 27
PCM1802DBG4: SSOP (DB), 20 pins · 65 per tube; lead finish Call TI; -40 to 85 °C. · p. 27
PCM1802DBR: SSOP (DB), 20 pins · 2000 per large tape and reel; lead finish Call TI | Nipdau; -40 to 85 °C. · p. 27
PCM1802DBR.B: SSOP (DB), 20 pins · 2000 per large tape and reel; lead finish Call TI; -40 to 85 °C. · p. 27
PCM1802DBRG4.B: SSOP (DB), 20 pins · 2000 per large tape and reel; lead finish NIPDAU; -40 to 85 °C. · p. 27

Parameters

Architecture: Sigma-Delta
Current - Supply: 32.3mA
Current - Supply(Max): 40mA
Features: Power-down mode
Interface Type: I2S
Junction Temperature(Max): 150℃
Number of Channels: 2
Operating Temperature: -40℃~+85℃
Resolution (Bits): 24
Sampling Rate: 96000Hz
The Chip Type: Audio Analog-to-Digital Converter
Thermal Resistance(Junction to Ambient): 80.8℃/W
Thermal Resistance(Junction to Board): 37.6℃/W
Thermal Resistance(Junction to Case): 40℃/W
Voltage - Supply: 2.7V~5.5V
Voltage - Supply(Absolute Max): 6.5V

Order codes

PCM1802DBLCSC C1520787
PCM1802DBRLCSC C2866894

Pinout

The pins of the PCM1802DB
Pin	Name	Type
1	VINL	Unspecified
2	VINR	Unspecified
3	VREF1	Unspecified
4	VREF2	Unspecified
5	VCC	Unspecified
6	AGND	Unspecified
7	PDWN#	Unspecified
8	BYPAS	Unspecified
9	FSYNC	Unspecified
10	LRCK	Unspecified
11	BCK	Unspecified
12	DOUT	Unspecified
13	DGND	Unspecified
14	VDD	Unspecified
15	SCKI	Unspecified
16	OSR	Unspecified
17	FMT0	Unspecified
18	FMT1	Unspecified
19	MODE0	Unspecified
20	MODE1	Unspecified

Open-source boards using it

All 5

2 layers101.6 × 137.4 mm
Openxcvr
dawsonjon/OpenXcvr
Cost Effective HF transceiver based on max1000 FPGA module
155 parts38MIT
2 layers40 × 75 mm
Phone pcb
kangp3/phone
This is a repository containing some code artifacts but mostly testing fragments for a project to develop a device to connect landline phones to other landline phones via a private VoIP network.
29 parts11MIT
2 layers70 × 64.5 mm
Clockgen main board
GDH-Technologies/cx-clockgen
Essentially a fork of Rene Wolf's `cxadc-clock-generator-audio-adc` gitlab project
17 parts1
4 layers50 × 90 mm
Tuner pedal
kulovac/tuner-pedal
Source for my tuner pedal project from algorithm design to PCB implementation
108 parts
2 layers99.1 × 99.1 mm
RADIO
dawsonjon/OpenXcvr
Cost Effective HF transceiver based on max1000 FPGA module
148 parts38MIT

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Questions

Is there a KiCad symbol and footprint for the PCM1802DB?

Yes. The symbol is EasyEDA_Cloud:PCM1802DBR and the footprint Package_SO:SSOP-20_5.3x7.2mm_P0.65mm, both drawn on this page. PCBKit places them on a board for you when you design with it.

What package is the PCM1802DB?

SSOP-20, with 20 pins. Its footprint is drawn on this page.

Where is the PCM1802DB datasheet?

Texas Instruments publishes it: the Datasheet link on this page opens it.

Where can I order the PCM1802DB?

JLCPCB lists it as part C2866894, with 129 in stock; the sellers' links on this page open their listings.

What can replace the PCM1802DB?

Parts like it in the library: the AS8510-ASSP by Advanced Monolithic Systems, the WM8786GEDS/RV by Cirrus Logic, the MAX186AEAP+ by Maxim Integrated (Analog Devices) and the MAX186AEAP+T by Maxim Integrated (Analog Devices). Check their datasheets: a part that fits the footprint may still differ in its ratings.

Which open-source boards use the PCM1802DB?

5 boards in 4 repositories on GitHub; the most starred are listed on this page, with their KiCad files.

PCM1802DB

Overview

Symbol

Footprint

From the datasheet

What it is and has

Around it

Specifications

Pins, by the datasheet

Ordering codes, by the datasheet

Parameters

Order codes

Pinout

Open-source boards using it

Openxcvr

Phone pcb

Clockgen main board

Tuner pedal

RADIO

Show this part on your page

Questions

Is there a KiCad symbol and footprint for the PCM1802DB?

What package is the PCM1802DB?

Where is the PCM1802DB datasheet?

Where can I order the PCM1802DB?

What can replace the PCM1802DB?

Which open-source boards use the PCM1802DB?

Parts like it

AS8510-ASSP

WM8786GEDS/RV

MAX186AEAP+

MAX186AEAP+T

MAX186BCAP+

MAX186CCAP+T

MAX186CEAP+T

MAX186DCAP+