LP2950-33LPRE3

Texas InstrumentsExtended

-40℃~+125℃@(Tj) 1 100mA 3.3V 30V 380mV@(100mA) 75uA Fixed Over Current Protection、Over Temperature Protection Positive TO-92-2.54mm Voltage Regulators - Linear, Low Drop Out (LDO) Regulators ROHS

Datasheet JLCPCB LCSC

Part id: ti/LP2950-33LPRE3
Category: Voltage Regulators, Linear, Low Drop Out (LDO) Regulators
Package: TO-92-2.54mm
Pins: 3
In stock: 2,576 at JLCPCB (C133551)
Used on: 10 open-source boards

Overview

The LP2950-33LPRE3 is a voltage Regulators, Linear, Low Drop Out (LDO) Regulator made by Texas Instruments in a TO-92-2.54mm package with 3 pins. -40℃~+125℃@(Tj) 1 100mA 3.3V 30V 380mV@(100mA) 75uA Fixed Over Current Protection、Over Temperature Protection Positive TO-92-2.54mm Voltage Regulators - Linear, Low Drop Out (LDO) Regulators ROHS.

PCBKit's library has its KiCad symbol (Pinmap_Generic:Regulator_Linear_1OUT_2GND_3IN, from PCBKit's generic symbols) and its footprint (Package_TO_SOT_THT:TO-92_Inline_Wide, from KiCad's library), ready for a KiCad board. 2,576 are in stock at JLCPCB (part C133551). 10 open-source boards in 9 repositories on GitHub use it.

Symbol

Pinmap_Generic:Regulator_Linear_1OUT_2GND_3INFrom PCBKit's generic symbols

Footprint

Package_TO_SOT_THT:TO-92_Inline_WideFrom KiCad's library

From the datasheet

Supply, least: 2 V · VIN, recommended operating min · p. 5
Supply, most: 30 V · VIN, recommended operating max · p. 5
Supply, absolute maximum: 35 V · VIN, legacy chip absolute max · p. 4
Supply, absolute maximum: 42 V · VIN, new chip absolute max · p. 4
Junction, hottest: 125 °C · Junction temperature, recommended operating max · p. 5
Gives: 100 mA · IL, recommended continuous output max · p. 5
Output: 3.3 V · Fixed output, legacy chip, 25°C, IL = 100uA, typical · p. 5
Takes working: 75 µA · GND current, legacy chip, IL = 100uA, 25°C, typical · p. 7
Takes working: 50 µA · GND current, new chip, IL = 100uA, 25°C, typical · p. 7
Current limit: 160 mA · Legacy chip, VOUT = 0V, 25°C, typical · p. 7
Current limit: 180 mA · New chip, VOUT = 0V, 25°C, typical · p. 7
Dropout: 50 mV · Legacy chip, VIN = 2V, IL = 100uA, 25°C, typical · p. 6
Dropout: 380 mV · Legacy chip, VIN = 2V, IL = 100mA, 25°C, typical · p. 6
Dropout: 340 mV · New chip, VIN = 2V, IL = 100mA, 25°C, typical · p. 6
Junction to air (LP): 140 K/W · Legacy chip, junction-to-ambient · p. 5
Junction to air (LP): 132.6 K/W · New chip, junction-to-ambient · p. 5
Junction to case (LP): 114.4 K/W · New chip, junction-to-case top · p. 5
Junction to board (LP): 94.9 K/W · New chip, junction-to-board · p. 5

What it is and has

Output current: 100mA · p. 1
Protection: Output current limiting and thermal shutdown · p. 1
Package: LP (3-pin TO-92) · p. 1

Around it

cap 1µF or larger: between INPUT and GND; Recommended input capacitor. · p. 3
cap 2.2 µF: between OUTPUT and GND; Nominal recommended output capacitor; table range 1 to 100 uF. Place close to OUTPUT. Check effective capacitance after derating. · p. 5

Specifications

Parameter	Conditions	As printed	Page
Continuous input voltage (legacy chip) VIN	Legacy chip; over operating free-air temperature range	min -0.3 · max 35 V	4
Continuous input voltage (new chip) VIN	New chip; over operating free-air temperature range	min -0.3 · max 42 V	4
Output voltage VOUT	Maximum is VIN + 0.3V or 39V, whichever is smaller	min -0.3 V	4
Storage temperature Tstg		min -65 · max 150 °C	4
Electrostatic discharge V(ESD)	Legacy chip; Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins; magnitude	max 2500 V	4
Electrostatic discharge V(ESD)	New chip; Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins; magnitude	max 3000 V	4
Electrostatic discharge V(ESD)	Legacy chip; Charged device model (CDM), per JEDEC specification JESD22-C101, all pins; magnitude	max 1000 V	4
Electrostatic discharge V(ESD)	New chip; Charged device model (CDM), per JEDEC specification JESD22-C101, all pins; magnitude	max 1000 V	4
Input voltage VIN	Over operating free-air temperature range	min 2 · max 30 V	5
Output current IL	Over operating free-air temperature range	min 0 · max 100 mA	5
Output capacitor COUT	NOM column recorded as typ; effective output capacitance of 0.5uF minimum required for stability	min 1 · typ 2.2 · max 100 uF	5
Output capacitor ESR (legacy chip) COUT ESR	Legacy chip; minimum printed as 30m Ω	max 5 Ω	5
Output capacitor ESR (new chip) COUT ESR	New chip	min 0 · max 2 Ω	5
Input capacitor CIN	NOM column recorded as typ	typ 1 uF	5
Junction temperature TJ		min -40 · max 125 °C	5
Junction-to-ambient thermal resistance RθJA	Legacy Chip; LP; 3 PINS	typ 140 °C/W	5
Junction-to-ambient thermal resistance RθJA	New Chip; LP; 3 PINS	typ 132.6 °C/W	5
Junction-to-case (top) thermal resistance RθJC(top)	New Chip; LP; 3 PINS	typ 114.4 °C/W	5
Junction-to-board thermal resistance RθJB	New Chip; LP; 3 PINS	typ 94.9 °C/W	5
Junction-to-top characterization parameter ΨJT	New Chip; LP; 3 PINS	typ 26.9 °C/W	5
Junction-to-board characterization parameter ΨJB	New Chip; LP; 3 PINS	typ 94.9 °C/W	5
Output voltage	LP295x-33; legacy chip; TJ = 25°C; IL = 100uA; VIN = VOUT(nominal) + 1V; CL = 2.2uF	min 3.267 · typ 3.3 · max 3.333 V	5
Output voltage	LP295x-33; legacy chip; TJ = –40°C to 125°C; IL = 100uA; VIN = VOUT(nominal) + 1V; CL = 2.2uF	min 3.234 · typ 3.3 · max 3.366 V	5
Output voltage	LP295x-33; new chip; TJ = 25°C; IL = 100uA; VIN = VOUT(nominal) + 1V; CL = 1uF	min 3.2868 · typ 3.3 · max 3.3132 V	5
Output voltage	LP295x-33; new chip; TJ = –40°C to 125°C; IL = 100uA; VIN = VOUT(nominal) + 1V; CL = 1uF	min 3.2736 · typ 3.3 · max 3.3264 V	5
Output voltage accuracy	New chip; VIN = [VOUT(NOM) + 1V] to 30V; IL = 100uA to 100mA; TJ = –40°C to 125°C	min -1 · max 1 %	6
Output voltage temperature coefficient	Legacy chip; IL = 100uA; TJ = –40°C to 125°C	typ 20 · max 100 ppm/°C	6
Output voltage temperature coefficient	New chip; IL = 100uA; TJ = –40°C to 125°C	typ 20 · max 60 ppm/°C	6
Line regulation	Legacy chip; VIN = [VOUT(NOM) + 1V] to 30V; TJ = 25°C	typ 0.03 · max 0.2 %/V	6
Line regulation	Legacy chip; VIN = [VOUT(NOM) + 1V] to 30V; TJ = –40°C to 125°C	max 0.4 %/V	6
Line regulation	New chip; VIN = [VOUT(NOM) + 1V] to 30V; TJ = 25°C	typ 0.0006 · max 0.01 %/V	6
Line regulation	New chip; VIN = [VOUT(NOM) + 1V] to 30V; TJ = –40°C to 125°C	max 0.015 %/V	6
Load regulation	Legacy chip; IL = 100uA to 100mA; TJ = 25°C	typ 0.04 · max 0.2 %	6
Load regulation	Legacy chip; IL = 100uA to 100mA; TJ = –40°C to 125°C	max 0.3 %	6
Load regulation	New chip; IL = 100uA to 100mA; TJ = 25°C	typ 0.04 · max 0.1 %	6
Load regulation	New chip; IL = 100uA to 100mA; TJ = –40°C to 125°C	max 0.2 %	6
Dropout voltage	Legacy chip; VIN = 2V; IL = 100uA; TJ = 25°C	typ 50 · max 80 mV	6
Dropout voltage	Legacy chip; VIN = 2V; IL = 100uA; TJ = –40°C to 125°C	max 150 mV	6
Dropout voltage	New chip; VIN = 2V; IL = 100uA; TJ = 25°C	typ 1 · max 4 mV	6
Dropout voltage	Legacy chip; VIN = 2V; IL = 100mA; TJ = 25°C	typ 380 · max 450 mV	6
Dropout voltage	Legacy chip; VIN = 2V; IL = 100mA; TJ = –40°C to 125°C	max 600 mV	6
Dropout voltage	New chip; VIN = 2V; IL = 100mA; TJ = 25°C	typ 340 · max 420 mV	6
Dropout voltage	New chip; VIN = 2V; IL = 100mA; TJ = –40°C to 125°C	max 570 mV	6
GND current	Legacy chip; IL = 100uA; TJ = 25°C	typ 75 · max 120 uA	7
GND current	Legacy chip; IL = 100uA; TJ = –40°C to 125°C	max 140 uA	7
GND current	New chip; IL = 100uA; TJ = 25°C	typ 50 · max 65 uA	7
GND current	New chip; IL = 100uA; TJ = –40°C to 125°C	max 80 uA	7
GND current	Legacy chip; IL = 100mA; TJ = 25°C	typ 8 · max 12 mA	7
GND current	Legacy chip; IL = 100mA; TJ = –40°C to 125°C	max 14 mA	7
GND current	New chip; IL = 100mA; TJ = 25°C	max 0.8 mA	7
GND current	New chip; IL = 100mA; TJ = –40°C to 125°C	max 0.9 mA	7
Dropout ground current	Legacy chip; VIN = VOUT(NOM) – 0.5V; IL = 100uA; TJ = 25°C	typ 110 · max 170 uA	7
Dropout ground current	Legacy chip; VIN = VOUT(NOM) – 0.5V; IL = 100uA; TJ = –40°C to 125°C	max 200 uA	7
Dropout ground current	New chip; VIN = VOUT(NOM) – 0.5V; IL = 100uA; TJ = 25°C	typ 78 · max 120 uA	7
Dropout ground current	New chip; VIN = VOUT(NOM) – 0.5V; IL = 100uA; TJ = –40°C to 125°C	max 150 uA	7
UVLO VIN rising	New chip; IL = 100uA; TJ = –40°C to 125°C	min 1.8 · typ 1.9 · max 2 V	7
UVLO VIN falling	New chip; IL = 100uA; TJ = –40°C to 125°C	min 1.7 · typ 1.8 · max 1.9 V	7
Hysteresis	UVLO; new chip; IL = 100uA; TJ = –40°C to 125°C	typ 100 mV	7
Current limit	Legacy chip; VOUT = 0V; TJ = 25°C	typ 160 · max 200 mA	7
Current limit	Legacy chip; VOUT = 0V; TJ = –40°C to 125°C	max 220 mA	7
Current limit	New chip; VOUT = 0V; TJ = 25°C	typ 180 · max 200 mA	7
Current limit	New chip; VOUT = 0V; TJ = –40°C to 125°C	max 230 mA	7
Thermal regulation	Legacy chip; IL = 100uA; TJ = 25°C	typ 0.05 · max 0.2 %/W	7
Thermal regulation	New chip; IL = 100uA; TJ = 25°C	typ 0.05 · max 0.2 %/W	7
Output noise (RMS), 10Hz to 100kHz	Legacy chip; CL = 200uF; TJ = 25°C	typ 160 uV	7
Output noise (RMS), 10Hz to 100kHz	New chip; CL = 100uF; TJ = 25°C	typ 250 uV	7
Power-supply ripple rejection	New chip; VIN - VOUT = 1V; frequency = 100Hz; IOUT ≥ 5mA; TJ = 25°C	typ 80 dB	7

Pins, by the datasheet

1 OUTPUT: Regulated output. A capacitor to GND is required for stability; place it as close to the output as possible. · p. 3
2 GND: Ground. · p. 3
3 INPUT: Input supply pin. A capacitor of 1uF or larger to ground is recommended. · p. 3

Parameters

Current Limit: 160mA
Features: Thermal shutdown
Junction Temperature(Max): 125℃
Noise: 430uV
Number of Outputs: 1
Operating Temperature: -40℃~+125℃@(Tj)
Output Configuration: Positive
Output Current: 100mA
Output Type: Fixed
Output Voltage: 3.3V
Thermal Resistance(Junction to Ambient): 140℃/W
Thermal Resistance(Junction to Board): 94.9℃/W
Thermal Resistance(Junction to Case): 114.4℃/W
Voltage - Supply: 2V~30V
Voltage - Supply(Absolute Max): 35V
Voltage Dropout: 380mV@(100mA)
standby current: 75uA

Order codes

LP2950-33LPRE3LCSC C133551

Pinout

The pins of the LP2950-33LPRE3
Pin	Name	Type
1	OUT	Power out
2	GND	Power in
3	IN	Power in

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Open-source boards using it

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Parts like it

Questions

Is there a KiCad symbol and footprint for the LP2950-33LPRE3?

Yes. The symbol is Pinmap_Generic:Regulator_Linear_1OUT_2GND_3IN and the footprint Package_TO_SOT_THT:TO-92_Inline_Wide, both drawn on this page. PCBKit places them on a board for you when you design with it.

What package is the LP2950-33LPRE3?

TO-92-2.54mm, with 3 pins. Its footprint is drawn on this page.

Where is the LP2950-33LPRE3 datasheet?

Texas Instruments publishes it: the Datasheet link on this page opens it.

Where can I order the LP2950-33LPRE3?

JLCPCB lists it as part C133551, with 2,576 in stock; the sellers' links on this page open their listings.

What can replace the LP2950-33LPRE3?

Parts like it in the library: the AMS1117-3.3 by Advanced Monolithic Systems, the AMS1117-3.3 by UMW, the XC6206P332MR by UMW and the XC6206P332MR-MS by MSKSEMI. Check their datasheets: a part that fits the footprint may still differ in its ratings.

Which open-source boards use the LP2950-33LPRE3?

10 boards in 9 repositories on GitHub; the most starred are listed on this page, with their KiCad files.

LP2950-33LPRE3

Overview

Symbol

Footprint

From the datasheet

What it is and has

Around it

Specifications

Pins, by the datasheet

Open-source boards using it

ECE445L Lab6

Lab6

Cjh4858 gam3769 project

Baseline project

Senior Design

Lab6

ECE445L Lab7

ECE445L Starter

Parts like it

AMS1117-3.3

AMS1117-3.3

XC6206P332MR

XC6206P332MR-MS