4 layers250.4 × 131 mm
Panel-16
geezacoleman/owl-driver-board
Development of a board that receives GPIO input and allows on/off control of connected solenoids.
939 parts14MIT
LM73100RPW
Texas InstrumentsExtended
-40℃~+125℃ 1 15V 2.7V~23V 28.4mV 426uA 44.85mΩ Integrated FET Reverse current blocking、Reverse polarity protection、Overvoltage lockout、Under-voltage lockout、Over temperature protection、Short-Circuit Protection、With enable VQFN-10-HR(2x2) ORing Controllers ROHS
- Part id
- ti/LM73100RPW
- Category
- Power Distribution Switches
- Package
- VQFN-10-HR(2x2)
- Pins
- 10
- In stock
- 13,401 at JLCPCB (C3210761)
- Used on
- 7 open-source boards
Overview
The LM73100RPW is a power Distribution Switche made by Texas Instruments in a VQFN-10-HR(2x2) package with 10 pins. -40℃~+125℃ 1 15V 2.7V~23V 28.4mV 426uA 44.85mΩ Integrated FET Reverse current blocking、Reverse polarity protection、Overvoltage lockout、Under-voltage lockout、Over temperature protection、Short-Circuit Protection、With enable VQFN-10-HR(2x2) ORing Controllers ROHS.
PCBKit's library has its KiCad symbol (LM73100:LM73100, from Antmicro) and its footprint (vqfn-hr-10-2x2mm:VQFN-HR-10_2x2mm, from Antmicro), ready for a KiCad board. 13,401 are in stock at JLCPCB (part C3210761). 7 open-source boards in 3 repositories on GitHub use it.
Symbol
Footprint
From the datasheet
11- Supply, least
- 2.7 V · IN, recommended operating minimum · p. 5
- Supply, most
- 23 V · IN, recommended operating maximum · p. 5
- Supply, absolute maximum
- 28 V · IN, absolute maximum at –40 ℃ ≤ TJ ≤ 125 ℃ · p. 4
- Junction, hottest
- 125 °C · Maximum recommended junction temperature · p. 5
- Takes working
- 426 µA · IN, typical quiescent current at VIN = 12 V, output enabled · p. 6
- Takes asleep
- 4.6 µA · IN, typical shutdown current, VEN < VSD(F) · p. 6
- Gives
- 5.5 A · Maximum continuous switch current, TJ ≤ 125 ℃ · p. 5
- Junction to air (RPW (QFN))
- 41.7 K/W · Custom 4-layer PCB with 8 thermal vias · p. 5
- Junction to air (RPW (QFN))
- 74.5 K/W · JEDEC 4-layer PCB with no thermal vias · p. 5
- Junction to board (RPW (QFN))
- 20 K/W · ΨJB, custom 4-layer PCB with 8 thermal vias · p. 5
- Junction to board (RPW (QFN))
- 27.6 K/W · ΨJB, JEDEC 4-layer PCB with no thermal vias · p. 5
What it is and has
10- Integrated FETs
- Back-to-back FETs · p. 1
- Reverse current protection
- Ideal diode operation with true reverse current blocking · p. 1
- Overvoltage protection
- Adjustable overvoltage lockout · p. 1
- Current monitor
- Analog load-current monitor output (IMON) · p. 1
- Current monitor range
- 0.5A to 5.5A · p. 1
- Current monitor accuracy
- ±15% maximum, IOUT ≥ 1A · p. 1
- Output slew rate
- Adjustable dVdt control · p. 1
- Protection
- Overtemperature protection · p. 1
- Power good
- PG indication with adjustable PGTH threshold · p. 1
- Package
- QFN, 2mm x 2mm, 0.45mm pitch · p. 1
Around it
4- res 350 kΩ minimum
- between IN and EN/UVLO; Pull-up for supply voltages greater than 5V or systems exposed to input reverse polarity. · p. 5
- res 350 kΩ minimum
- between IN and PGTH; Use when referred to input supply in systems exposed to input reverse polarity. · p. 5
- diode Clamp below 1.8 V
- between IMON and GND; Recommended zener diode to clamp IMON during high-current transients. · p. 21
- cap 3300 pF
- between DVDT and GND; CdVdt in the typical 12 V adapter protection application. · p. 28
Specifications
118| Parameter | Conditions | As printed | Page |
|---|---|---|---|
| Maximum Input Voltage Range, –40 ℃ ≤ TJ ≤ 125 ℃ VIN | IN; minimum = max (–15, VOUT - 21) | max 28 V | 4 |
| Maximum Input Voltage Range, –10 ℃ ≤ TJ ≤ 125 ℃ VIN | IN; minimum = max (–15, VOUT - 22) | max 28 V | 4 |
| Maximum Output Voltage Range, –40 ℃ ≤ TJ ≤ 125 ℃ VOUT | OUT; maximum = min (28, VIN + 21) | min -0.3 V | 4 |
| Maximum Output Voltage Range, –10 ℃ ≤ TJ ≤ 125 ℃ VOUT | OUT; maximum = min (28, VIN + 22) | min -0.3 V | 4 |
| Minimum Output Voltage Pulse (< 1 us) VOUT,PLS | OUT | min -0.8 V | 4 |
| Maximum Enable Pin Voltage Range VEN/UVLO | EN/UVLO; footnote (2) | min -0.3 · max 6.5 V | 4 |
| Maximum OVLO Pin Voltage Range VOVLO | OVLO; footnote (2) | min -0.3 · max 6.5 V | 4 |
| Maximum PGTH Pin Voltage Range VPGTH | PGTH; footnote (2) | min -0.3 · max 6.5 V | 4 |
| Maximum PG Pin Voltage Range VPG | PG | min -0.3 · max 6.5 V | 4 |
| Maximum IMON Pin Voltage Range VIMON | IMON | max 1.8 V | 4 |
| Maximum Continuous Switch Current IMAX | IN to OUT; value printed in MIN column | min 5.5 A | 4 |
| Maximum Lead Temperature TLEAD | max 300 °C | 4 | |
| Storage temperature TSTG | min -65 · max 150 °C | 4 | |
| Electrostatic discharge V(ESD) | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins; rating ±2000 V | min -2000 · max 2000 V | 4 |
| Electrostatic discharge V(ESD) | Charged device model (CDM), per JEDEC specification JESD22-C101, all pins; rating ±500 V | min -500 · max 500 V | 4 |
| Input Voltage Range VIN | IN | min 2.7 · max 23 V | 5 |
| Enable Pin Voltage Range VEN/UVLO | EN/UVLO; footnote (2) | max 5 V | 5 |
| OVLO Pin Voltage Range VOVLO | OVLO | min 0.5 · max 1.5 V | 5 |
| PGTH Pin Voltage Range VPGTH | PGTH; footnote (3) | max 5 V | 5 |
| PG Pin Voltage Range VPG | PG; footnote (3) | max 5 V | 5 |
| IMON Pin Voltage VIMON | IMON | max 1.5 V | 5 |
| Continuous Switch Current, , TJ ≤ 125 ℃ IMAX | IN to OUT | max 5.5 A | 5 |
| Junction temperature TJ | min -40 · max 125 °C | 5 | |
| Junction-to-ambient thermal resistance RθJA | LM73100, RPW (QFN), 10 PINS; custom 4-layer PCB (2s2p), 8 thermal vias under device | typ 41.7 °C/W | 5 |
| Junction-to-ambient thermal resistance RθJA | LM73100, RPW (QFN), 10 PINS; JEDEC 4-layer PCB (2s2p), no thermal vias under device | typ 74.5 °C/W | 5 |
| Junction-to-top characterization parameter ΨJT | LM73100, RPW (QFN), 10 PINS | typ 1 °C/W | 5 |
| Junction-to-board characterization parameter ΨJB | LM73100, RPW (QFN), 10 PINS; custom 4-layer PCB (2s2p), 8 thermal vias under device | typ 20 °C/W | 5 |
| Junction-to-board characterization parameter ΨJB | LM73100, RPW (QFN), 10 PINS; JEDEC 4-layer PCB (2s2p), no thermal vias under device | typ 27.6 °C/W | 5 |
| IN supply UVP rising threshold VUVP(R) | min 2.44 · typ 2.53 · max 2.64 V | 6 | |
| IN supply UVP falling threshold VUVP(F) | min 2.35 · typ 2.42 · max 2.55 V | 6 | |
| IN supply quiescent current IQ(ON) | VIN = 2.7 V | typ 347 · max 492 uA | 6 |
| IN supply quiescent current IQ(ON) | VIN = 12 V | typ 426 · max 509 uA | 6 |
| IN supply quiescent current IQ(ON) | VIN = 23 V | typ 459 · max 612 uA | 6 |
| IN supply quiescent current during RCB IQ(RCB) | VOUT > VIN | typ 189.7 · max 234 uA | 6 |
| IN supply disabled state current IQ(OFF) | VSD(F) < VEN < VUVLO(R) | typ 74.5 · max 97.6 uA | 6 |
| IN supply shutdown current ISD | VEN < VSD(F) | typ 4.6 · max 8.2 uA | 6 |
| IN supply OFF state current IQ(OVLO) | OVLO condition, VOUT > VIN | typ 191 uA | 6 |
| IN supply leakage current IINLKG(IRPP) | VIN = –14 V, VOUT = 0 V | typ -3.5 uA | 6 |
| ON RESISTANCE (IN - OUT) RON | VIN = 12 V, IOUT = 3 A, TJ = 25 ℃ | typ 28.4 mΩ | 6 |
| ON RESISTANCE (IN - OUT) RON | 2.7 ≤ VIN ≤ 23 V, –40 ℃ ≤ TJ ≤ 125 ℃ | max 44.85 mΩ | 6 |
| EN/UVLO rising threshold VUVLO(R) | min 1.183 · typ 1.2 · max 1.223 V | 6 | |
| EN/UVLO falling threshold VUVLO(F) | min 1.076 · typ 1.09 · max 1.116 V | 6 | |
| EN/UVLO falling threshold for lowest shutdown current VSD(F) | min 0.45 · typ 0.74 V | 6 | |
| EN/UVLO leakage current IENLKG | min -0.1 · max 0.1 uA | 6 | |
| OVLO rising threshold VOV(R) | min 1.183 · typ 1.2 · max 1.223 V | 6 | |
| OVLO falling threshold VOV(F) | min 1.076 · typ 1.09 · max 1.116 V | 6 | |
| OVLO pin leakage current IOVLKG | 0.5 V < VOVLO < 1.5 V | min -0.1 · max 0.1 uA | 6 |
| OUT leakage current IOUTLKG(OVLO) | OVLO condition, VOUT > VIN | typ 317 uA | 6 |
| Fixed fast-trip current threshold IFT | typ 21.9 A | 6 | |
| Analog load current monitor gain (IMON : IOUT) GIMON | IOUT = 0.5 A to 1A | min 144 · typ 181 · max 216 uA/A | 6 |
| Analog load current monitor gain (IMON : IOUT) GIMON | IOUT = 1 A to 5.5 A | min 153 · typ 181 · max 207 uA/A | 6 |
| (VIN - VOUT) forward regulation voltage VFWD | IOUT = 10 mA | min 4.8 · typ 16.4 · max 28.4 mV | 6 |
| (VOUT - VIN) threshold for fast BFET turn off (enter reverse current blocking) VREVTH | min 22.7 · typ 29.3 · max 36.5 mV | 6 | |
| (VIN - VOUT) threshold for fast BFET turn on (exit reverse current blocking) VFWDTH | min 85.9 · typ 105.8 · max 125 mV | 6 | |
| Reverse leakage current (unpowered condition) IREVLKG(OFF) | VOUT = 12 V, VIN = 0 V | typ 4.8 uA | 6 |
| Reverse leakage current IREVLKG | (VOUT - VIN) = 21.5 V | typ 10.1 · max 15.86 uA | 6 |
| OUT leakage current during RCB state while ON IOUTLKG(RCB) | (VOUT - VIN) = 1 V | typ 247.6 · max 322 uA | 6 |
| PG pin low voltage while de-asserted VPGD | VIN < VUVP(F), VEN < VSD, IPG = 26 uA | typ 0.67 · max 0.9 V | 7 |
| PG pin low voltage while de-asserted VPGD | VIN < VUVP(F), VEN < VSD, IPG = 242 uA | typ 0.78 · max 1 V | 7 |
| PG pin low voltage while de-asserted VPGD | VIN > VUVP(R) | max 0.6 V | 7 |
| PG pin leakage current while asserted IPGLKG | typ 0.5 · max 2 uA | 7 | |
| PGTH rising threshold VPGTH(R) | min 1.183 · typ 1.2 · max 1.223 V | 7 | |
| PGTH falling threshold VPGTH(F) | min 1.076 · typ 1.09 · max 1.116 V | 7 | |
| PGTH leakage current IPGTHLKG | min -1 · max 1 uA | 7 | |
| Thermal shutdown rising threshold, TJ↑ TSD | typ 154 °C | 7 | |
| Thermal shutdown hysteresis, TJ↓ TSDHYS | typ 10 °C | 7 | |
| dVdt pin charging current IdVdt | min 1.15 · typ 2.34 · max 3.66 uA | 7 | |
| Overvoltage lock-out response time tOVLO | VOVLO > VOV(R) to VOUT↓ | typ 1.1 us | 7 |
| Fixed fast-trip response time tFT | IOUT > IFT to IOUT↓ | typ 500 ns | 7 |
| Reverse Current Blocking recovery time tSWRCB | (VIN - VOUT) > VFWDTH to VOUT ↑ | typ 50 us | 7 |
| Reverse Current Blocking fast comparator response time tRCB | (VOUT - VIN) > 1.3 x VREVTH to BFET OFF | typ 1 us | 7 |
| PG Assertion de-glitch tPGA | typ 12 us | 7 | |
| PG De-assertion de-glitch tPGD | typ 12 us | 7 | |
| Output Rising slew rate SRON | VIN = 2.7 V, CdVdt = Open; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 12.14 V/ms | 8 |
| Output Rising slew rate SRON | VIN = 2.7 V, CdVdt = 1800 pF; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 0.87 V/ms | 8 |
| Output Rising slew rate SRON | VIN = 2.7 V, CdVdt = 3300 pF; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 0.5 V/ms | 8 |
| Output Rising slew rate SRON | VIN = 12 V, CdVdt = Open; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 28.1 V/ms | 8 |
| Output Rising slew rate SRON | VIN = 12 V, CdVdt = 1800 pF; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 1.09 V/ms | 8 |
| Output Rising slew rate SRON | VIN = 12 V, CdVdt = 3300 pF; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 0.61 V/ms | 8 |
| Output Rising slew rate SRON | VIN = 23 V, CdVdt = Open; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 44.78 V/ms | 8 |
| Output Rising slew rate SRON | VIN = 23 V, CdVdt = 1800 pF; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 1.25 V/ms | 8 |
| Output Rising slew rate SRON | VIN = 23 V, CdVdt = 3300 pF; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 0.71 V/ms | 8 |
| Turn on delay tD,ON | VIN = 2.7 V, CdVdt = Open; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 0.09 ms | 8 |
| Turn on delay tD,ON | VIN = 2.7 V, CdVdt = 1800 pF; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 0.6 ms | 8 |
| Turn on delay tD,ON | VIN = 2.7 V, CdVdt = 3300 pF; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 0.97 ms | 8 |
| Turn on delay tD,ON | VIN = 12 V, CdVdt = Open; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 0.1 ms | 8 |
| Turn on delay tD,ON | VIN = 12 V, CdVdt = 1800 pF; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 1.32 ms | 8 |
| Turn on delay tD,ON | VIN = 12 V, CdVdt = 3300 pF; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 2.35 ms | 8 |
| Turn on delay tD,ON | VIN = 23 V, CdVdt = Open; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 0.11 ms | 8 |
| Turn on delay tD,ON | VIN = 23 V, CdVdt = 1800 pF; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 1.99 ms | 8 |
| Turn on delay tD,ON | VIN = 23 V, CdVdt = 3300 pF; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 3.69 ms | 8 |
| Rise time tR | VIN = 2.7 V, CdVdt = Open; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 0.17 ms | 8 |
| Rise time tR | VIN = 2.7 V, CdVdt = 1800 pF; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 2.51 ms | 8 |
| Rise time tR | VIN = 2.7 V, CdVdt = 3300 pF; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 4.33 ms | 8 |
| Rise time tR | VIN = 12 V, CdVdt = Open; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 0.35 ms | 8 |
| Rise time tR | VIN = 12 V, CdVdt = 1800 pF; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 8.1 ms | 8 |
| Rise time tR | VIN = 12 V, CdVdt = 3300 pF; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 15.37 ms | 8 |
| Rise time tR | VIN = 23 V, CdVdt = Open; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 0.4 ms | 8 |
| Rise time tR | VIN = 23 V, CdVdt = 1800 pF; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 14.4 ms | 8 |
| Rise time tR | VIN = 23 V, CdVdt = 3300 pF; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 25.89 ms | 8 |
| Turn on time tON | VIN = 2.7 V, CdVdt = Open; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 0.27 ms | 8 |
| Turn on time tON | VIN = 2.7 V, CdVdt = 1800 pF; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 3.11 ms | 8 |
| Turn on time tON | VIN = 2.7 V, CdVdt = 3300 pF; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 5.31 ms | 8 |
| Turn on time tON | VIN = 12 V, CdVdt = Open; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 0.45 ms | 8 |
| Turn on time tON | VIN = 12 V, CdVdt = 1800 pF; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 10.08 ms | 8 |
| Turn on time tON | VIN = 12 V, CdVdt = 3300 pF; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 17.72 ms | 8 |
| Turn on time tON | VIN = 23 V, CdVdt = Open; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 0.5 ms | 8 |
| Turn on time tON | VIN = 23 V, CdVdt = 1800 pF; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 16.41 ms | 8 |
| Turn on time tON | VIN = 23 V, CdVdt = 3300 pF; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 29.57 ms | 8 |
| Turn off delay tD,OFF | VIN = 2.7 V, CdVdt = Open; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 64.44 us | 8 |
| Turn off delay tD,OFF | VIN = 2.7 V, CdVdt = 1800 pF; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 64.44 us | 8 |
| Turn off delay tD,OFF | VIN = 2.7 V, CdVdt = 3300 pF; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 64.44 us | 8 |
| Turn off delay tD,OFF | VIN = 12 V, CdVdt = Open; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 25.32 us | 8 |
| Turn off delay tD,OFF | VIN = 12 V, CdVdt = 1800 pF; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 25.32 us | 8 |
| Turn off delay tD,OFF | VIN = 12 V, CdVdt = 3300 pF; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 25.32 us | 8 |
| Turn off delay tD,OFF | VIN = 23 V, CdVdt = Open; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 23.02 us | 8 |
| Turn off delay tD,OFF | VIN = 23 V, CdVdt = 1800 pF; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 23.02 us | 8 |
| Turn off delay tD,OFF | VIN = 23 V, CdVdt = 3300 pF; TJ = 25°C, RL = 100 Ω, COUT = 1 uF | typ 23.02 us | 8 |
Pins, by the datasheet
10- 1 EN/UVLO
- Active-high enable; a divider from input supply to GND adjusts undervoltage lockout. Do not leave floating. · p. 3
- 2 OVLO
- A divider from supply to GND adjusts overvoltage lockout; also serves as active-low enable. Do not leave floating. · p. 3
- 3 PG
- Power-good indication asserted high when the internal power path is fully on and PGTH exceeds its threshold. · p. 3
- 4 PGTH
- Power-good threshold input. · p. 3
- 5 IN
- Power Input. · p. 3
- 6 OUT
- Power Output. · p. 3
- 7 DVDT
- A capacitor to GND sets output turn-on slew rate; leave floating for the fastest turn-on slew rate. · p. 3
- 8 GND
- Ground reference for all internal circuits; connect to system GND. · p. 3
- 9 IMON
- Analog load-current monitor output; a resistor to ground sets gain. Use an external clamp for large current spikes; connect to ground if unused and do not leave floating. · p. 3
- 10 DNC
- Internal test pin; do not connect anything. · p. 3
Open-source boards using it
7- 4 layers50.5 × 80 mm
- 4 layers100 × 60 mm
- 2 layers65 × 56 mm
Owl driver board
geezacoleman/owl-driver-board
Development of a board that receives GPIO input and allows on/off control of connected solenoids.
182 parts14MIT - 4 layers234.4 × 56 mm
Owl driver board-16
geezacoleman/owl-driver-board
Development of a board that receives GPIO input and allows on/off control of connected solenoids.
469 parts14MIT - 2 layers81 × 131 mm
Panel
geezacoleman/owl-driver-board
Development of a board that receives GPIO input and allows on/off control of connected solenoids.
355 parts14MIT - 2 layers149 × 131 mm
Panel
geezacoleman/owl-driver-board
Development of a board that receives GPIO input and allows on/off control of connected solenoids.
717 parts14MIT
Questions
Is there a KiCad symbol and footprint for the LM73100RPW?
Yes. The symbol is LM73100:LM73100 and the footprint vqfn-hr-10-2x2mm:VQFN-HR-10_2x2mm, both drawn on this page. PCBKit places them on a board for you when you design with it.
What package is the LM73100RPW?
VQFN-10-HR(2x2), with 10 pins. Its footprint is drawn on this page.
Where is the LM73100RPW datasheet?
Texas Instruments publishes it: the Datasheet link on this page opens it.
Where can I order the LM73100RPW?
JLCPCB lists it as part C3210761, with 13,401 in stock; the sellers' links on this page open their listings.
Which open-source boards use the LM73100RPW?
7 boards in 3 repositories on GitHub; the most starred are listed on this page, with their KiCad files.