4 layers77 × 62.5 mm
Models
philipturner/capacitive-displacement-metrology
Objective: Finish a project that has dragged on for 14 months.
82 parts6MIT
ISO7761DW
Texas InstrumentsExtended
-55℃~+125℃ 1 100Mbps 100kV/us 11ns 2.25V~5.5V 2.25V~5.5V 5 5000 High Level SOIC-16-300mil Digital Isolators ROHS
- Part id
- ti/ISO7761DW
- Category
- Digital Isolators
- Package
- SOIC-16-300mil
- Pins
- 16
- In stock
- 200 at JLCPCB (C2871529)
- Used on
- 4 open-source boards
Overview
The ISO7761DW is a digital Isolator made by Texas Instruments in a SOIC-16-300mil package with 16 pins. -55℃~+125℃ 1 100Mbps 100kV/us 11ns 2.25V~5.5V 2.25V~5.5V 5 5000 High Level SOIC-16-300mil Digital Isolators ROHS.
PCBKit's library has its KiCad symbol (Isolator:ISO7761DW, from KiCad's library) and its footprint (Package_SO:SOIC-16W_7.5x10.3mm_P1.27mm, from KiCad's library), ready for a KiCad board. 200 are in stock at JLCPCB (part C2871529). 4 open-source boards in 3 repositories on GitHub use it.
Symbol
Footprint
From the datasheet
17- Supply, least
- 2.25 V · VCC1, recommended operating min · p. 7
- Supply, most
- 5.5 V · VCC1, recommended operating max · p. 7
- Supply, absolute maximum
- 6 V · VCC1, absolute max · p. 6
- Works from
- -55 °C · TA, operating ambient min · p. 7
- Works up to
- 125 °C · TA, operating ambient max · p. 7
- Junction, hottest
- 150 °C · TJ, absolute max · p. 6
- A pin gives at most
- 15 mA · Output source or sink current, absolute max magnitude · p. 6
- Data rate, most
- 100 Mbit/s · Data rate max · p. 7
- Junction to air (DW (SOIC))
- 60.3 K/W · Junction-to-ambient thermal resistance · p. 8
- Junction to case (DW (SOIC))
- 24 K/W · Junction-to-case top thermal resistance · p. 8
- Junction to board (DW (SOIC))
- 29.3 K/W · Junction-to-board thermal resistance · p. 8
- Takes working
- 42 mA · sum of ICC1 and ICC2 typical; 5 V, 100 Mbps, all channels switching, CL = 15 pF · p. 13
- Takes at most
- 55.9 mA · sum of ICC1 and ICC2 max; 5 V, 100 Mbps, all channels switching, CL = 15 pF · p. 13
- Takes working
- 26.4 mA · sum of ICC1 and ICC2, typical at 2.5 V, 100 Mbps, CL = 15 pF · p. 17
- Takes at most
- 35.8 mA · sum of ICC1 and ICC2 maxima at 2.5 V, 100 Mbps, CL = 15 pF · p. 17
- Edge
- 1.1 ns · typical output rise time, 5-V supply · p. 19
- Edge
- 1 ns · typical output rise time, 3.3-V supply · p. 20
What it is and has
13- Data rate
- 100 Mbps · p. 1
- Supply range
- 2.25 V to 5.5 V · p. 1
- Level translation
- 2.25 V to 5.5 V · p. 1
- Operating temperature
- –55°C to +125°C · p. 1
- Propagation delay
- 11 ns typical at 5 V · p. 1
- Isolation lifetime
- >30 years projected · p. 1
- CMTI
- ±100 kV/μs typical · p. 1
- Isolation rating
- 5000 VRMS, DW-16, UL 1577 · p. 9
- Surge isolation voltage
- 12800 VPK, DW-16 · p. 9
- Isolation barrier lifetime
- >30 years projected · p. 1
- Surge capability
- Up to 12.8 kV · p. 1
- Default output
- High · p. 28
- Rated isolation
- 5000 VRMS / 7071 VPK, DW-16 · p. 28
Specifications
120| Parameter | Conditions | As printed | Page |
|---|---|---|---|
| Supply voltage (2) VCC1, VCC2 | min -0.5 · max 6 V | 6 | |
| Voltage at INx, OUTx V | Maximum VCCX + 0.5 V; maximum voltage must not exceed 6 V. | min -0.5 V | 6 |
| Output current Io | min -15 · max 15 mA | 6 | |
| Junction temperature TJ | max 150 °C | 6 | |
| Storage temperature Tstg | min -65 · max 150 °C | 6 | |
| Electrostatic discharge V(ESD) | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins; ±6000 V | max 6000 V | 6 |
| Electrostatic discharge V(ESD) | Charged device model (CDM), per JEDEC specification JESD22-C101, all pins; ±1500 V | max 1500 V | 6 |
| Electrostatic discharge V(ESD) | Contact discharge per IEC 61000-4-2; isolation barrier withstand test; ±8000 V | max 8000 V | 6 |
| Supply Voltage VCC1, VCC2 | min 2.25 · max 5.5 V | 7 | |
| UVLO threshold when supply voltage is rising Vcc (UVLO+) | NOM = 2 V | typ 2 · max 2.25 V | 7 |
| UVLO threshold when supply voltage is falling Vcc (UVLO-) | NOM = 1.8 V | min 1.7 · typ 1.8 V | 7 |
| Supply voltage UVLO hysteresis VHYS (UVLO) | NOM = 200 mV | min 100 · typ 200 mV | 7 |
| High level output current IOH | VCCO = 5 V | min -4 mA | 7 |
| High level output current IOH | VCCO = 3.3 V | min -2 mA | 7 |
| High level output current IOH | VCCO = 2.5 V | min -1 mA | 7 |
| Low level output current IOL | VCCO = 5 V | max 4 mA | 7 |
| Low level output current IOL | VCCO = 3.3 V | max 2 mA | 7 |
| Low level output current IOL | VCCO = 2.5 V | max 1 mA | 7 |
| Low level Input voltage VIL | Maximum 0.3 x VCCI | min 0 V | 7 |
| Data Rate DR(2) | min 0 · max 100 Mbps | 7 | |
| Ambient temperature TA | NOM = 25°C | min -55 · typ 25 · max 125 °C | 7 |
| Junction-to-ambient thermal resistance RθJA | DW (SOIC), 16 PINS | typ 60.3 °C/W | 8 |
| Junction-to-case (top) thermal resistance RθJC(top) | DW (SOIC), 16 PINS | typ 24 °C/W | 8 |
| Junction-to-board thermal resistance RθJB | DW (SOIC), 16 PINS | typ 29.3 °C/W | 8 |
| Junction-to-top characterization parameter ψJT | DW (SOIC), 16 PINS | typ 3.3 °C/W | 8 |
| Junction-to-board characterization parameter ψJB | DW (SOIC), 16 PINS | typ 28.7 °C/W | 8 |
| Maximum power dissipation (both sides) PD | ISO7761; VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, input a 50-MHz 50% duty cycle square wave | max 314 mW | 8 |
| Maximum power dissipation (side-1) PD1 | ISO7761; VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, input a 50-MHz 50% duty cycle square wave | max 88 mW | 8 |
| Maximum power dissipation (side-2) PD2 | ISO7761; VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, input a 50-MHz 50% duty cycle square wave | max 226 mW | 8 |
| External clearance(1) CLR | DW-16; shortest terminal-to-terminal distance through air; >8 mm | min 8 mm | 9 |
| External creepage(1) CPG | DW-16; shortest terminal-to-terminal distance across the package surface; >8 mm | min 8 mm | 9 |
| Distance through the insulation DTI | DW-16; minimum internal gap (internal clearance); >17 um | min 17 um | 9 |
| Comparative tracking index CTI | DW-16; DIN EN 60112 (VDE 0303-11); IEC 60112; UL 746A; >600 V | min 600 V | 9 |
| Maximum repetitive peak isolation voltage VIORM | DW-16; DIN EN IEC 60747-17 (VDE 0884-17); AC voltage (bipolar) | max 2121 VPK | 9 |
| Maximum working isolation voltage VIOWM | DW-16; AC voltage; time dependent dielectric breakdown (TDDB) test; see Figure 8-7 | max 1500 VRMS | 9 |
| Maximum working isolation voltage VIOWM | DW-16; DC voltage | max 2121 VDC | 9 |
| Maximum transient isolation voltage VIOTM | ISO7761, DW-16; VTEST = VIOTM, t = 60 s (qualification); VTEST = 1.2 x VIOTM, t = 1 s (100% production) | max 7071 VPK | 9 |
| Maximum impulse voltage(3) VIMP | DW-16; tested in air, 1.2/50-us waveform per IEC 62368-1 | max 8000 VPK | 9 |
| Maximum surge isolation voltage(4) VIOSM | DW-16; VIOSM ≥ 1.3 x VIMP; tested in oil (qualification test), 1.2/50-us waveform per IEC 62368-1 | max 12800 VPK | 9 |
| Apparent charge(5) qpd | DW-16; method a, after input-output safety test subgroup 2/3; Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 x VIORM, tm = 10 s | max 5 pC | 9 |
| Apparent charge(5) qpd | DW-16; method a, after environmental tests subgroup 1; Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 x VIORM, tm = 10 s | max 5 pC | 9 |
| Apparent charge(5) qpd | DW-16; method b, routine test (100% production) and preconditioning (type test); Vini = 1.2 x VIOTM, tini = 1 s; Vpd(m) = 1.875 x VIORM, tm = 1 s (method b1) or Vpd(m) = Vini, tm = tini (method b2) | max 5 pC | 9 |
| Barrier capacitance, input to output(6) CIO | DW-16; VIO = 0.4 x sin (2πft), f = 1 MHz; approximately 1.1 pF | typ 1.1 pF | 9 |
| Pollution degree | DW-16; value 2 | typ 2 | 9 |
| Maximum withstanding isolation voltage VISO | DW-16; UL 1577; VTEST = VISO, t = 60 s (qualification); VTEST = 1.2 x VISO, t = 1 s (100% production) | max 5000 VRMS | 9 |
| Safety input, output, or supply current (1) IS | DW-16 PACKAGE; RθJA = 60.3°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C; see Figure 5-1 | max 377 mA | 11 |
| Safety input, output, or supply current (1) IS | DW-16 PACKAGE; RθJA = 60.3°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C; see Figure 5-1 | max 576 mA | 11 |
| Safety input, output, or supply current (1) IS | DW-16 PACKAGE; RθJA = 60.3°C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C; see Figure 5-1 | max 754 mA | 11 |
| Safety input, output, or total power (1) PS | DW-16 PACKAGE; RθJA = 60.3°C/W, TJ = 150°C, TA = 25°C; see Figure 5-3 | max 2073 mW | 11 |
| Maximum safety temperature (1) TS | DW-16 PACKAGE | max 150 °C | 11 |
| High-level output voltage VOH | VCC1 = VCC2 = 5 V ± 10%; IOH = -4 mA; see Figure 6-1; minimum VCCO - 0.4 V | typ 4.8 V | 13 |
| Low-level output voltage VOL | VCC1 = VCC2 = 5 V ± 10%; IOL = 4 mA; see Figure 6-1 | typ 0.2 · max 0.4 V | 13 |
| High-level input current IIH | VCC1 = VCC2 = 5 V ± 10%; VIH = VCCI at INx | max 10 uA | 13 |
| Low-level input current IIL | VCC1 = VCC2 = 5 V ± 10%; VIL = 0 V at INx | min -10 uA | 13 |
| Common mode transient immunity CMTI | VCC1 = VCC2 = 5 V ± 10%; VI = VCCI or 0 V, VCM = 1200 V; see Figure 6-3 | min 85 · typ 100 kV/us | 13 |
| Input Capacitance (2) CI | VI = VCC/ 2 + 0.4 × sin(2πft), f = 1 MHz, VCC = 5 V; measured from input pin to same side ground | typ 2 pF | 13 |
| Supply current - DC signal ICC1 | ISO7761; VCC1 = VCC2 = 5 V ±10%; VI = VCCI | typ 1.9 · max 3.5 mA | 13 |
| Supply current - DC signal ICC2 | ISO7761; VCC1 = VCC2 = 5 V ±10%; VI = VCCI | typ 2.9 · max 5.4 mA | 13 |
| Supply current - DC signal ICC1 | ISO7761; VCC1 = VCC2 = 5 V ±10%; VI = 0 V | typ 7.3 · max 10.6 mA | 13 |
| Supply current - DC signal ICC2 | ISO7761; VCC1 = VCC2 = 5 V ±10%; VI = 0 V | typ 4.2 · max 6.9 mA | 13 |
| Supply current - AC signal ICC1 | ISO7761; VCC1 = VCC2 = 5 V ±10%; 1 Mbps; all channels switching with square wave clock input; CL = 15 pF | typ 4.7 · max 6.6 mA | 13 |
| Supply current - AC signal ICC2 | ISO7761; VCC1 = VCC2 = 5 V ±10%; 1 Mbps; all channels switching with square wave clock input; CL = 15 pF | typ 3.8 · max 6.5 mA | 13 |
| Supply current - AC signal ICC1 | ISO7761; VCC1 = VCC2 = 5 V ±10%; 10 Mbps; all channels switching with square wave clock input; CL = 15 pF | typ 5.3 · max 8 mA | 13 |
| Supply current - AC signal ICC2 | ISO7761; VCC1 = VCC2 = 5 V ±10%; 10 Mbps; all channels switching with square wave clock input; CL = 15 pF | typ 6.3 · max 9.6 mA | 13 |
| Supply current - AC signal ICC1 | ISO7761; VCC1 = VCC2 = 5 V ±10%; 100 Mbps; all channels switching with square wave clock input; CL = 15 pF | typ 11.5 · max 15.6 mA | 13 |
| Supply current - AC signal ICC2 | ISO7761; VCC1 = VCC2 = 5 V ±10%; 100 Mbps; all channels switching with square wave clock input; CL = 15 pF | typ 30.5 · max 40.3 mA | 13 |
| High-level output voltage VOH | VCC1 = VCC2 = 3.3 V ±10%; IOH = -2mA; see Figure 6-1; minimum VCCO - 0.3 V | typ 3.2 V | 15 |
| Low-level output voltage VOL | VCC1 = VCC2 = 3.3 V ±10%; IOL = 2mA; see Figure 6-1 | typ 0.1 · max 0.3 V | 15 |
| High-level input current IIH | VCC1 = VCC2 = 3.3 V ±10%; VIH = VCCI at INx | max 10 uA | 15 |
| Low-level input current IIL | VCC1 = VCC2 = 3.3 V ±10%; VIL = 0 V at INx | min -10 uA | 15 |
| Common mode transient immunity CMTI | VCC1 = VCC2 = 3.3 V ±10%; VI = VCC or 0 V, VCM = 1200 V; see Figure 6-3 | min 85 · typ 100 kV/us | 15 |
| Supply current - DC signal ICC1 | ISO7761; VCC1 = VCC2 = 3.3 V ±10%; VI = VCCI | typ 1.8 · max 3.5 mA | 15 |
| Supply current - DC signal ICC2 | ISO7761; VCC1 = VCC2 = 3.3 V ±10%; VI = VCCI | typ 2.9 · max 5.3 mA | 15 |
| Supply current - DC signal ICC1 | ISO7761; VCC1 = VCC2 = 3.3 V ±10%; VI = 0 V | typ 7.2 · max 10.3 mA | 15 |
| Supply current - DC signal ICC2 | ISO7761; VCC1 = VCC2 = 3.3 V ±10%; VI = 0 V | typ 4.2 · max 6.9 mA | 15 |
| Supply current - AC signal ICC1 | ISO7761; VCC1 = VCC2 = 3.3 V ±10%; 1 Mbps; all channels switching with square wave clock input; CL = 15 pF | typ 4.6 · max 6.5 mA | 15 |
| Supply current - AC signal ICC2 | ISO7761; VCC1 = VCC2 = 3.3 V ±10%; 1 Mbps; all channels switching with square wave clock input; CL = 15 pF | typ 3.7 · max 6.3 mA | 15 |
| Supply current - AC signal ICC1 | ISO7761; VCC1 = VCC2 = 3.3 V ±10%; 10 Mbps; all channels switching with square wave clock input; CL = 15 pF | typ 5.1 · max 7.5 mA | 15 |
| Supply current - AC signal ICC2 | ISO7761; VCC1 = VCC2 = 3.3 V ±10%; 10 Mbps; all channels switching with square wave clock input; CL = 15 pF | typ 5.5 · max 8.6 mA | 15 |
| Supply current - AC signal ICC1 | ISO7761; VCC1 = VCC2 = 3.3 V ±10%; 100 Mbps; all channels switching with square wave clock input; CL = 15 pF | typ 9.4 · max 12.7 mA | 15 |
| Supply current - AC signal ICC2 | ISO7761; VCC1 = VCC2 = 3.3 V ±10%; 100 Mbps; all channels switching with square wave clock input; CL = 15 pF | typ 22.8 · max 30.5 mA | 15 |
| High-level output voltage VOH | VCC1 = VCC2 = 2.5 V ±10%; IOH = -1mA; See Figure 6-1; minimum = VCCO - 0.2 V | typ 2.45 V | 17 |
| Low-level output voltage VOL | VCC1 = VCC2 = 2.5 V ±10%; IOL = 1mA; See Figure 6-1 | typ 0.05 · max 0.2 V | 17 |
| High-level input current IIH | VCC1 = VCC2 = 2.5 V ±10%; VIH = VCCI at INx | max 10 uA | 17 |
| Low-level input current IIL | VCC1 = VCC2 = 2.5 V ±10%; VIL = 0 V at INx | min -10 uA | 17 |
| Common mode transient immunity CMTI | VCC1 = VCC2 = 2.5 V ±10%; VI = VCC or 0 V, VCM = 1200 V; See Figure 6-3 | min 85 · typ 100 kV/us | 17 |
| Supply current - DC signal ICC1 | ISO7761; VCC1 = VCC2 = 2.5 V ±10%; VI = VCCI | typ 1.8 · max 3.4 mA | 17 |
| Supply current - DC signal ICC2 | ISO7761; VCC1 = VCC2 = 2.5 V ±10%; VI = VCCI | typ 2.9 · max 5.3 mA | 17 |
| Supply current - DC signal ICC1 | ISO7761; VCC1 = VCC2 = 2.5 V ±10%; VI = 0 V | typ 7.2 · max 10.3 mA | 17 |
| Supply current - DC signal ICC2 | ISO7761; VCC1 = VCC2 = 2.5 V ±10%; VI = 0 V | typ 4.2 · max 6.8 mA | 17 |
| Supply current - AC signal ICC1 | ISO7761; VCC1 = VCC2 = 2.5 V ±10%; all channels switching with square wave clock input; CL = 15 pF; 1 Mbps | typ 4.6 · max 6.5 mA | 17 |
| Supply current - AC signal ICC2 | ISO7761; VCC1 = VCC2 = 2.5 V ±10%; all channels switching with square wave clock input; CL = 15 pF; 1 Mbps | typ 3.7 · max 6.3 mA | 17 |
| Supply current - AC signal ICC1 | ISO7761; VCC1 = VCC2 = 2.5 V ±10%; all channels switching with square wave clock input; CL = 15 pF; 10 Mbps | typ 4.9 · max 7.2 mA | 17 |
| Supply current - AC signal ICC2 | ISO7761; VCC1 = VCC2 = 2.5 V ±10%; all channels switching with square wave clock input; CL = 15 pF; 10 Mbps | typ 5 · max 7.9 mA | 17 |
| Supply current - AC signal ICC1 | ISO7761; VCC1 = VCC2 = 2.5 V ±10%; all channels switching with square wave clock input; CL = 15 pF; 100 Mbps | typ 8.3 · max 11.2 mA | 17 |
| Supply current - AC signal ICC2 | ISO7761; VCC1 = VCC2 = 2.5 V ±10%; all channels switching with square wave clock input; CL = 15 pF; 100 Mbps | typ 18.1 · max 24.6 mA | 17 |
| Propagation delay time tPLH, tPHL | VCC1 = VCC2 = 5 V ±10%; See Figure 6-1 | min 6 · typ 11 · max 17 ns | 19 |
| Pulse width distortion(1) |tPHL – tPLH| PWD | VCC1 = VCC2 = 5 V ±10%; See Figure 6-1 | typ 0.4 · max 5.9 ns | 19 |
| Channel-to-channel output skew time(2) tsk(o) | VCC1 = VCC2 = 5 V ±10%; Same-direction channels | max 4 ns | 19 |
| Part-to-part skew time(3) tsk(pp) | VCC1 = VCC2 = 5 V ±10% | max 4.5 ns | 19 |
| Output signal rise time tr | VCC1 = VCC2 = 5 V ±10%; See Figure 6-1 | typ 1.1 · max 3.9 ns | 19 |
| Output signal fall time tf | VCC1 = VCC2 = 5 V ±10%; See Figure 6-1 | typ 1.4 · max 3.9 ns | 19 |
| Default output delay time from input power loss tDO | VCC1 = VCC2 = 5 V ±10%; measured from the time VCC goes below 1.7V; See Figure 6-2 | typ 0.2 · max 0.3 us | 19 |
| Time interval error tie | VCC1 = VCC2 = 5 V ±10%; 216 – 1 PRBS data at 100 Mbps | typ 1.3 ns | 19 |
| Propagation delay time tPLH, tPHL | VCC1 = VCC2 = 3.3 V ±10%; See Figure 6-1 | min 6 · typ 12 · max 18.5 ns | 20 |
| Pulse width distortion(1) |tPHL – tPLH| PWD | VCC1 = VCC2 = 3.3 V ±10%; See Figure 6-1 | typ 0.5 · max 5.9 ns | 20 |
| Channel-to-channel output skew time(2) tsk(o) | VCC1 = VCC2 = 3.3 V ±10%; Same-direction channels | max 4.4 ns | 20 |
| Part-to-part skew time(3) tsk(pp) | VCC1 = VCC2 = 3.3 V ±10% | max 5 ns | 20 |
| Output signal rise time tr | VCC1 = VCC2 = 3.3 V ±10%; See Figure 6-1 | typ 1 · max 3 ns | 20 |
| Output signal fall time tf | VCC1 = VCC2 = 3.3 V ±10%; See Figure 6-1 | typ 1 · max 3 ns | 20 |
| Default output delay time from input power loss tDO | VCC1 = VCC2 = 3.3 V ±10%; measured from the time VCC goes below 1.7V; See Figure 6-2 | typ 0.2 · max 0.3 us | 20 |
| Time interval error tie | VCC1 = VCC2 = 3.3 V ±10%; 216 – 1 PRBS data at 100 Mbps | typ 1.3 ns | 20 |
| Propagation delay time tPLH, tPHL | VCC1 = VCC2 = 2.5 V ±10%; See Figure 6-1 | min 7.5 · typ 13 · max 21 ns | 21 |
| Pulse width distortion(1) |tPHL – tPLH| PWD | VCC1 = VCC2 = 2.5 V ±10%; See Figure 6-1 | typ 0.6 · max 5.9 ns | 21 |
| Channel-to-channel output skew time(2) tsk(o) | VCC1 = VCC2 = 2.5 V ±10%; Same-direction channels | max 4.4 ns | 21 |
| Part-to-part skew time(3) tsk(pp) | VCC1 = VCC2 = 2.5 V ±10% | max 5.3 ns | 21 |
| Output signal rise time tr | VCC1 = VCC2 = 2.5 V ±10%; See Figure 6-1 | typ 1 · max 3.5 ns | 21 |
| Output signal fall time tf | VCC1 = VCC2 = 2.5 V ±10%; See Figure 6-1 | typ 1 · max 3.5 ns | 21 |
| Default output delay time from input power loss tDO | VCC1 = VCC2 = 2.5 V ±10%; measured from the time VCC goes below 1.7V; See Figure 6-2 | typ 0.1 · max 0.3 us | 21 |
| Time interval error tie | VCC1 = VCC2 = 2.5 V ±10%; 216 – 1 PRBS data at 100 Mbps | typ 1.3 ns | 21 |
Open-source boards using it
4- 4 layers130 × 130 mm
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FT2232H USB to JTAG and UART
Shahrukh-13/FT2232H_USB_to_JTAG_and_UART
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16 parts - 4 layers77 × 62.5 mm
MainBoard2
philipturner/capacitive-displacement-metrology
Objective: Finish a project that has dragged on for 14 months.
75 parts6MIT
Parts like it
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Questions
Is there a KiCad symbol and footprint for the ISO7761DW?
Yes. The symbol is Isolator:ISO7761DW and the footprint Package_SO:SOIC-16W_7.5x10.3mm_P1.27mm, both drawn on this page. PCBKit places them on a board for you when you design with it.
What package is the ISO7761DW?
SOIC-16-300mil, with 16 pins. Its footprint is drawn on this page.
Where is the ISO7761DW datasheet?
Texas Instruments publishes it: the Datasheet link on this page opens it.
Where can I order the ISO7761DW?
JLCPCB lists it as part C2871529, with 200 in stock; the sellers' links on this page open their listings.
What can replace the ISO7761DW?
Parts like it in the library: the ISO7741DW by Texas Instruments, the SSP5840ED by Shanghai Siproin Microelectronics, the ISO7740DW by Texas Instruments and the ISO7760FDWR by Texas Instruments. Check their datasheets: a part that fits the footprint may still differ in its ratings.
Which open-source boards use the ISO7761DW?
4 boards in 3 repositories on GitHub; the most starred are listed on this page, with their KiCad files.