Overview
The ISO7741BDW is a digital Isolator made by Texas Instruments in a SOIC-16-300mil package with 16 pins. -55℃~+125℃ 1 10.7ns 100Mbps 100kV/us 2.25V~5.5V 2.25V~5.5V 3 5000 SOIC-16-300mil Digital Isolators ROHS.
PCBKit's library has its KiCad symbol (EasyEDA_Cloud:XISO6041HDFPR, from EasyEDA) and its footprint (Package_SO:SOIC-16W_7.5x10.3mm_P1.27mm, from KiCad's library), ready for a KiCad board. 2,262 are in stock at JLCPCB (part C2862696).
Symbol
Footprint
From the datasheet
16- Supply, least
- 2.25 V · VCC1, recommended operating min · p. 7
- Supply, most
- 5.5 V · VCC1, recommended operating max · p. 7
- Supply, absolute maximum
- 6 V · VCC1, absolute max · p. 6
- Works from
- -55 °C · TA, operating ambient min · p. 7
- Works up to
- 125 °C · TA, operating ambient max · p. 7
- Junction, hottest
- 150 °C · TJ, absolute max · p. 6
- A pin gives at most
- 15 mA · IO, source or sink absolute max · p. 6
- Takes working
- 6 mA · sum of ICC1 and ICC2, typical, 5 V, 1 Mbps, all channels switching, CL = 15 pF · p. 14
- Takes at most
- 39.4 mA · sum of ICC1 and ICC2, max, 5 V, 100 Mbps, all channels switching, CL = 15 pF · p. 14
- Junction to air (DW (SOIC))
- 83.4 K/W · junction-to-ambient thermal resistance · p. 8
- Junction to case (DW (SOIC))
- 46 K/W · junction-to-case top thermal resistance · p. 8
- Junction to board (DW (SOIC))
- 48 K/W · junction-to-board thermal resistance · p. 8
- Data rate, most
- 100 Mbit/s · maximum specified data rate · p. 7
- Takes working
- 23 mA · sum of ICC1 and ICC2, typical at 3.3 V, all channels switching at 100 Mbps, CL = 15 pF · p. 16
- Takes at most
- 30.5 mA · sum of ICC1 and ICC2, max at 3.3 V, all channels switching at 100 Mbps, CL = 15 pF · p. 16
- Edge
- 600 ps · typical output rise time, VCC1 = VCC2 = 3.3 V ±10% · p. 20
What it is and has
9- Data rate
- 100Mbps · p. 1
- Level translation
- 2.25V to 5.5V · p. 1
- Insulation
- Basic insulation · p. 2
- Isolation barrier
- Double capacitive silicon dioxide (SiO2) · p. 2
- Data rate
- 100 Mbps · p. 1
- Level translation
- 2.25 V to 5.5 V · p. 1
- Common mode transient immunity
- ±100 kV/μs typical · p. 1
- Default output
- High · p. 28
- Package
- DW-16 · p. 28
Specifications
149| Parameter | Conditions | As printed | Page |
|---|---|---|---|
| Supply voltage VCC1, VCC2 | Relative to local ground | min -0.5 · max 6 V | 6 |
| Voltage at INx, OUTx, ENx V | Maximum VCCX + 0.5 V; must not exceed 6 V | min -0.5 V | 6 |
| Output current IO | min -15 · max 15 mA | 6 | |
| Junction temperature TJ | max 150 °C | 6 | |
| Storage temperature Tstg | min -65 · max 150 °C | 6 | |
| Electrostatic discharge V(ESD) | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins; ±6000 V | max 6000 V | 6 |
| Electrostatic discharge V(ESD) | Charged device model (CDM), per JEDEC specification JESD22-C101, all pins; ±1500 V | max 1500 V | 6 |
| Electrostatic discharge V(ESD) | Contact discharge per IEC 61000-4-2; isolation barrier withstand test; ±7000 V | max 7000 V | 6 |
| Supply Voltage VCC1, VCC2 | Over operating free-air temperature range | min 2.25 · max 5.5 V | 7 |
| UVLO threshold when supply voltage is rising VCC(UVLO+) | 2 V nominal | typ 2 · max 2.25 V | 7 |
| UVLO threshold when supply voltage is falling VCC(UVLO-) | 1.8 V nominal | min 1.7 · typ 1.8 V | 7 |
| Supply voltage UVLO hysteresis VHYS(UVLO) | 200 mV nominal | min 100 · typ 200 mV | 7 |
| High level output current IOH | VCCO = 5 V | min -4 mA | 7 |
| High level output current IOH | VCCO = 3.3 V | min -2 mA | 7 |
| High level output current IOH | VCCO = 2.5 V | min -1 mA | 7 |
| Low level output current IOL | VCCO = 5 V | max 4 mA | 7 |
| Low level output current IOL | VCCO = 3.3 V | max 2 mA | 7 |
| Low level output current IOL | VCCO = 2.5 V | max 1 mA | 7 |
| Low level Input voltage VIL | Maximum 0.3 x VCCI | min 0 V | 7 |
| Data Rate DR | Footnote states 100 Mbps maximum specified data rate | max 50 Mbps | 7 |
| Ambient temperature TA | 25 °C nominal | min -55 · typ 25 · max 125 °C | 7 |
| Junction-to-ambient thermal resistance RθJA | DW (SOIC), 16 PINS | typ 83.4 °C/W | 8 |
| Junction-to-case (top) thermal resistance RθJC(top) | DW (SOIC), 16 PINS | typ 46 °C/W | 8 |
| Junction-to-board thermal resistance RθJB | DW (SOIC), 16 PINS | typ 48 °C/W | 8 |
| Junction-to-top characterization parameter ψJT | DW (SOIC), 16 PINS | typ 19.1 °C/W | 8 |
| Junction-to-board characterization parameter ψJB | DW (SOIC), 16 PINS | typ 47.5 °C/W | 8 |
| Maximum power dissipation (both sides) PD | ISO7741; VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, input a 50-MHz 50% duty cycle square wave | max 215 mW | 8 |
| Maximum power dissipation (side-1) PD1 | ISO7741; VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, input a 50-MHz 50% duty cycle square wave | max 75 mW | 8 |
| Maximum power dissipation (side-2) PD2 | ISO7741; VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, input a 50-MHz 50% duty cycle square wave | max 140 mW | 8 |
| External clearance CLR | DW-16; shortest terminal-to-terminal distance through air; >8 mm | min 8 mm | 9 |
| External creepage CPG | DW-16; shortest terminal-to-terminal distance across the package surface; >8 mm | min 8 mm | 9 |
| Distance through the insulation DTI | DW-16; minimum internal gap (internal clearance); >17 um | min 17 um | 9 |
| Comparative tracking index CTI | DW-16; DIN EN 60112 (VDE 0303-11); IEC 60112; >600 V | min 600 V | 9 |
| Maximum repetitive peak isolation voltage VIORM | ISO7741B, DW-16; AC voltage (bipolar) | max 1414 VPK | 9 |
| Maximum working isolation voltage VIOWM | ISO7741B, DW-16; AC voltage; time dependent dielectric breakdown (TDDB) test; see Figure 8-7 | max 1000 VRMS | 9 |
| Maximum working isolation voltage VIOWM | ISO7741B, DW-16; DC voltage | max 1414 VDC | 9 |
| Maximum transient isolation voltage VIOTM | DW-16; VTEST = VIOTM, t = 60 s qualification; VTEST = 1.2 x VIOTM, t = 1 s, 100% production | max 8000 VPK | 9 |
| Maximum impulse voltage VIMP | ISO7741B, DW-16; tested in air, 1.2/50-us waveform per IEC 62368-1 | max 6000 VPK | 9 |
| Maximum surge isolation voltage VIOSM | ISO7741B, DW-16; VIOSM ≥ 1.3 x VIMP; tested in oil, qualification test, 1.2/50-us waveform per IEC 62368-1 | max 7800 VPK | 9 |
| Apparent charge qpd | DW-16; method a, after input-output safety test subgroup 2/3; Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 x VIORM, tm = 10 s | max 5 pC | 9 |
| Apparent charge qpd | ISO7741B, DW-16; method a, after environmental tests subgroup 1; Vini = VIOTM, tini = 60 s; Vpd(m) = 1.3 x VIORM, tm = 10 s | max 5 pC | 9 |
| Apparent charge qpd | ISO7741B, DW-16; method b, routine test and preconditioning; Vini = 1.2 x VIOTM, tini = 1 s; Vpd(m) = 1.5 x VIORM, tm = 1 s (method b1), or Vpd(m) = Vini, tm = tini (method b2) | max 5 pC | 9 |
| Barrier capacitance, input to output CIO | DW-16; VIO = 0.4 x sin (2πft), f = 1 MHz; approximately 1 pF | typ 1 pF | 9 |
| Pollution degree | DW-16; value 2 | typ 2 | 9 |
| Safety input, output, or supply current IS | DW-16; RθJA = 83.4°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C; see Figure 5-1 | max 273 mA | 12 |
| Safety input, output, or supply current IS | DW-16; RθJA = 83.4°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C; see Figure 5-1 | max 416 mA | 12 |
| Safety input, output, or supply current IS | DW-16; RθJA = 83.4°C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C; see Figure 5-1 | max 545 mA | 12 |
| Safety input, output, or total power PS | DW-16; RθJA = 83.4°C/W, TJ = 150°C, TA = 25°C; see Figure 5-3 | max 1499 mW | 12 |
| Maximum safety temperature TS | DW-16 | max 150 °C | 12 |
| High-level output voltage VOH | VCC1 = VCC2 = 5 V ±10%; IOH = -4 mA; see Figure 6-1; minimum VCCO - 0.4 V | typ 4.8 V | 13 |
| Low-level output voltage VOL | VCC1 = VCC2 = 5 V ±10%; IOL = 4 mA; see Figure 6-1 | typ 0.2 · max 0.4 V | 13 |
| High-level input current IIH | VCC1 = VCC2 = 5 V ±10%; VIH = VCCI at INx | max 10 uA | 13 |
| Low-level input current IIL | VCC1 = VCC2 = 5 V ±10%; VIL = 0 V at INx | min -10 uA | 13 |
| High-level input current IIH | VCC1 = VCC2 = 5 V ±10%; VIH = VCCI at ENx | max 20 uA | 13 |
| Low-level input current IIL | VCC1 = VCC2 = 5 V ±10%; VIL = 0 V at ENx | min -20 uA | 13 |
| Common mode transient immunity CMTI | VCC1 = VCC2 = 5 V ±10%; VI = VCCI or 0 V, VCM = 1200 V; see Figure 6-4 | min 85 · typ 100 kV/us | 13 |
| Input Capacitance CI | VI = VCC/ 2 + 0.4×sin(2πft), f = 1 MHz, VCC = 5 V; measured from input pin to same side ground | typ 2 pF | 13 |
| Supply current - Disable ICC1 | ISO7741, VCC1 = VCC2 = 5 V ±10%; EN1 = EN2 = 0 V; VI = VCCI; without F suffix | typ 1 · max 2.2 mA | 14 |
| Supply current - Disable ICC2 | ISO7741, VCC1 = VCC2 = 5 V ±10%; EN1 = EN2 = 0 V; VI = VCCI; without F suffix | typ 0.8 · max 1.6 mA | 14 |
| Supply current - Disable ICC1 | ISO7741, VCC1 = VCC2 = 5 V ±10%; EN1 = EN2 = 0 V; VI = 0 V; without F suffix | typ 4.3 · max 6.3 mA | 14 |
| Supply current - Disable ICC2 | ISO7741, VCC1 = VCC2 = 5 V ±10%; EN1 = EN2 = 0 V; VI = 0 V; without F suffix | typ 1.8 · max 2.8 mA | 14 |
| Supply current - DC signal ICC1 | ISO7741, VCC1 = VCC2 = 5 V ±10%; EN1 = EN2 = VCCI; VI = VCCI; without F suffix | typ 1.5 · max 2.9 mA | 14 |
| Supply current - DC signal ICC2 | ISO7741, VCC1 = VCC2 = 5 V ±10%; EN1 = EN2 = VCCI; VI = VCCI; without F suffix | typ 2 · max 3.7 mA | 14 |
| Supply current - DC signal ICC1 | ISO7741, VCC1 = VCC2 = 5 V ±10%; EN1 = EN2 = VCCI; VI = 0 V; without F suffix | typ 4.8 · max 6.8 mA | 14 |
| Supply current - DC signal ICC2 | ISO7741, VCC1 = VCC2 = 5 V ±10%; EN1 = EN2 = VCCI; VI = 0 V; without F suffix | typ 3.2 · max 5.2 mA | 14 |
| Supply current - AC signal ICC1 | ISO7741, VCC1 = VCC2 = 5 V ±10%; 1 Mbps; all channels switching with square wave clock input; CL = 15 pF | typ 3.2 · max 4.8 mA | 14 |
| Supply current - AC signal ICC2 | ISO7741, VCC1 = VCC2 = 5 V ±10%; 1 Mbps; all channels switching with square wave clock input; CL = 15 pF | typ 2.8 · max 4.6 mA | 14 |
| Supply current - AC signal ICC1 | ISO7741, VCC1 = VCC2 = 5 V ±10%; 10 Mbps; all channels switching with square wave clock input; CL = 15 pF | typ 3.7 · max 5.5 mA | 14 |
| Supply current - AC signal ICC2 | ISO7741, VCC1 = VCC2 = 5 V ±10%; 10 Mbps; all channels switching with square wave clock input; CL = 15 pF | typ 4.2 · max 6.4 mA | 14 |
| Supply current - AC signal ICC1 | ISO7741, VCC1 = VCC2 = 5 V ±10%; 100 Mbps; all channels switching with square wave clock input; CL = 15 pF | typ 11.4 · max 14.4 mA | 14 |
| Supply current - AC signal ICC2 | ISO7741, VCC1 = VCC2 = 5 V ±10%; 100 Mbps; all channels switching with square wave clock input; CL = 15 pF | typ 21 · max 25 mA | 14 |
| High-level output voltage VOH | VCC1 = VCC2 = 3.3 V ±10%; IOH = -2mA; see Figure 6-1; minimum VCCO - 0.3 V | typ 3.2 V | 15 |
| Low-level output voltage VOL | VCC1 = VCC2 = 3.3 V ±10%; IOL = 2mA; see Figure 6-1 | typ 0.1 · max 0.3 V | 15 |
| High-level input current IIH | VCC1 = VCC2 = 3.3 V ±10%; VIH = VCCI at INx | max 10 uA | 15 |
| Low-level input current IIL | VCC1 = VCC2 = 3.3 V ±10%; VIL = 0 V at INx | min -10 uA | 15 |
| High-level input current IIH | VCC1 = VCC2 = 3.3 V ±10%; VIH = VCCI at ENx | max 30 uA | 15 |
| Low-level input current IIL | VCC1 = VCC2 = 3.3 V ±10%; VIL = 0 V at ENx | min -30 uA | 15 |
| Common mode transient immunity CMTI | VCC1 = VCC2 = 3.3 V ±10%; VI = VCCI or 0 V, VCM = 1200 V; see Figure 6-4 | min 85 · typ 100 kV/us | 15 |
| Supply current - Disable ICC1 | ISO7741; VCC1 = VCC2 = 3.3 V ±10%; EN1 = EN2 = 0 V; VI = VCCI | typ 1 · max 2.1 mA | 16 |
| Supply current - Disable ICC2 | ISO7741; VCC1 = VCC2 = 3.3 V ±10%; EN1 = EN2 = 0 V; VI = VCCI | typ 0.8 · max 1.5 mA | 16 |
| Supply current - Disable ICC1 | ISO7741; VCC1 = VCC2 = 3.3 V ±10%; EN1 = EN2 = 0 V; VI = 0 V | typ 4.3 · max 6.3 mA | 16 |
| Supply current - Disable ICC2 | ISO7741; VCC1 = VCC2 = 3.3 V ±10%; EN1 = EN2 = 0 V; VI = 0 V | typ 1.9 · max 2.7 mA | 16 |
| Supply current - DC signal ICC1 | ISO7741; VCC1 = VCC2 = 3.3 V ±10%; EN1 = EN2 = VCCI; VI = VCCI | typ 1.5 · max 2.8 mA | 16 |
| Supply current - DC signal ICC2 | ISO7741; VCC1 = VCC2 = 3.3 V ±10%; EN1 = EN2 = VCCI; VI = VCCI | typ 2 · max 3.7 mA | 16 |
| Supply current - DC signal ICC1 | ISO7741; VCC1 = VCC2 = 3.3 V ±10%; EN1 = EN2 = VCCI; VI = 0 V | typ 4.8 · max 6.8 mA | 16 |
| Supply current - DC signal ICC2 | ISO7741; VCC1 = VCC2 = 3.3 V ±10%; EN1 = EN2 = VCCI; VI = 0 V | typ 3.2 · max 5.1 mA | 16 |
| Supply current - AC signal ICC1 | ISO7741; VCC1 = VCC2 = 3.3 V ±10%; all channels switching with square wave clock input; CL = 15 pF; 1 Mbps | typ 3.2 · max 4.7 mA | 16 |
| Supply current - AC signal ICC2 | ISO7741; VCC1 = VCC2 = 3.3 V ±10%; all channels switching with square wave clock input; CL = 15 pF; 1 Mbps | typ 2.7 · max 4.5 mA | 16 |
| Supply current - AC signal ICC1 | ISO7741; VCC1 = VCC2 = 3.3 V ±10%; all channels switching with square wave clock input; CL = 15 pF; 10 Mbps | typ 3.5 · max 5.2 mA | 16 |
| Supply current - AC signal ICC2 | ISO7741; VCC1 = VCC2 = 3.3 V ±10%; all channels switching with square wave clock input; CL = 15 pF; 10 Mbps | typ 3.7 · max 5.8 mA | 16 |
| Supply current - AC signal ICC1 | ISO7741; VCC1 = VCC2 = 3.3 V ±10%; all channels switching with square wave clock input; CL = 15 pF; 100 Mbps | typ 8 · max 11 mA | 16 |
| Supply current - AC signal ICC2 | ISO7741; VCC1 = VCC2 = 3.3 V ±10%; all channels switching with square wave clock input; CL = 15 pF; 100 Mbps | typ 15 · max 19.5 mA | 16 |
| High-level output voltage VOH | VCC1 = VCC2 = 2.5 V ±10%; IOH = -1mA; See Figure 6-1; minimum = VCCO - 0.2 | typ 2.45 V | 17 |
| Low-level output voltage VOL | VCC1 = VCC2 = 2.5 V ±10%; IOL = 1mA; See Figure 6-1 | typ 0.05 · max 0.2 V | 17 |
| High-level input current IIH | VCC1 = VCC2 = 2.5 V ±10%; VIH = VCCI at INx | max 10 uA | 17 |
| Low-level input current IIL | VCC1 = VCC2 = 2.5 V ±10%; VIL = 0 V at INx | min -10 uA | 17 |
| High-level input current IIH | VCC1 = VCC2 = 2.5 V ±10%; VIH = VCCI at ENx | max 30 uA | 17 |
| Low-level input current IIL | VCC1 = VCC2 = 2.5 V ±10%; VIL = 0 V at ENx | min -30 uA | 17 |
| Common mode transient immunity CMTI | VCC1 = VCC2 = 2.5 V ±10%; VI = VCCI or 0 V, VCM = 1200 V; See Figure 6-4 | min 85 · typ 100 kV/us | 17 |
| Supply current - Disable ICC1 | ISO7741; VCC1 = VCC2 = 2.5 V ±10%; EN1 = EN2 = 0 V; VI = VCCI | typ 1.5 · max 2.2 mA | 18 |
| Supply current - Disable ICC2 | ISO7741; VCC1 = VCC2 = 2.5 V ±10%; EN1 = EN2 = 0 V; VI = VCCI | typ 0.8 · max 2.8 mA | 18 |
| Supply current - Disable ICC1 | ISO7741; VCC1 = VCC2 = 2.5 V ±10%; EN1 = EN2 = 0 V; VI = 0 V | typ 4.3 · max 6.3 mA | 18 |
| Supply current - Disable ICC2 | ISO7741; VCC1 = VCC2 = 2.5 V ±10%; EN1 = EN2 = 0 V; VI = 0 V | typ 1.8 · max 2.8 mA | 18 |
| Supply current - DC signal ICC1 | ISO7741; VCC1 = VCC2 = 2.5 V ±10%; EN1 = EN2 = VCCI; VI = VCCI | typ 1.4 · max 2.9 mA | 18 |
| Supply current - DC signal ICC2 | ISO7741; VCC1 = VCC2 = 2.5 V ±10%; EN1 = EN2 = VCCI; VI = VCCI | typ 2 · max 3.9 mA | 18 |
| Supply current - DC signal ICC1 | ISO7741; VCC1 = VCC2 = 2.5 V ±10%; EN1 = EN2 = VCCI; VI = 0 V | typ 4.7 · max 6.8 mA | 18 |
| Supply current - DC signal ICC2 | ISO7741; VCC1 = VCC2 = 2.5 V ±10%; EN1 = EN2 = VCCI; VI = 0 V | typ 3.2 · max 5.21 mA | 18 |
| Supply current - AC signal ICC1 | ISO7741; VCC1 = VCC2 = 2.5 V ±10%; all channels switching with square wave clock input; CL = 15 pF; 1 Mbps | typ 3.1 · max 4.8 mA | 18 |
| Supply current - AC signal ICC2 | ISO7741; VCC1 = VCC2 = 2.5 V ±10%; all channels switching with square wave clock input; CL = 15 pF; 1 Mbps | typ 2.7 · max 4.7 mA | 18 |
| Supply current - AC signal ICC1 | ISO7741; VCC1 = VCC2 = 2.5 V ±10%; all channels switching with square wave clock input; CL = 15 pF; 10 Mbps | typ 3.4 · max 5.2 mA | 18 |
| Supply current - AC signal ICC2 | ISO7741; VCC1 = VCC2 = 2.5 V ±10%; all channels switching with square wave clock input; CL = 15 pF; 10 Mbps | typ 3.5 · max 5.64 mA | 18 |
| Supply current - AC signal ICC1 | ISO7741; VCC1 = VCC2 = 2.5 V ±10%; all channels switching with square wave clock input; CL = 15 pF; 100 Mbps | typ 5.6 · max 8.7 mA | 18 |
| Supply current - AC signal ICC2 | ISO7741; VCC1 = VCC2 = 2.5 V ±10%; all channels switching with square wave clock input; CL = 15 pF; 100 Mbps | typ 10.8 · max 15 mA | 18 |
| Propagation delay time tPLH, tPHL | VCC1 = VCC2 = 5 V ±10%; See Figure 6-1 | min 6 · typ 12.7 · max 17 ns | 19 |
| Pulse width distortion(1) |tPHL – tPLH| PWD | VCC1 = VCC2 = 5 V ±10%; See Figure 6-1 | max 5.9 ns | 19 |
| Channel-to-channel output skew time(2) tsk(o) | VCC1 = VCC2 = 5 V ±10%; Same-direction channels | max 4 ns | 19 |
| Part-to-part skew time(3) tsk(pp) | VCC1 = VCC2 = 5 V ±10% | max 4.4 ns | 19 |
| Output signal rise time tr | VCC1 = VCC2 = 5 V ±10%; See Figure 6-1 | typ 1.1 · max 3.9 ns | 19 |
| Output signal fall time tf | VCC1 = VCC2 = 5 V ±10%; See Figure 6-1 | typ 1.1 · max 3.9 ns | 19 |
| Disable propagation delay, high-to-high impedance output tPHZ | VCC1 = VCC2 = 5 V ±10%; See Figure 6-2 | typ 14 · max 22 ns | 19 |
| Disable propagation delay, low-to-high impedance output tPLZ | VCC1 = VCC2 = 5 V ±10%; See Figure 6-2 | typ 13 · max 20 ns | 19 |
| Enable propagation delay, high impedance-to-high output for ISO774x tPZH | VCC1 = VCC2 = 5 V ±10%; See Figure 6-2; without F suffix | typ 11 · max 20 ns | 19 |
| Enable propagation delay, high impedance-to-low output for ISO774x tPZL | VCC1 = VCC2 = 5 V ±10%; See Figure 6-2; without F suffix | typ 2.5 · max 8.5 us | 19 |
| Default output delay time from input power loss tDO | VCC1 = VCC2 = 5 V ±10%; Measured from the time VCC goes below 1.7V. See Figure 6-4 | typ 0.1 · max 0.3 us | 19 |
| Time interval error tie | VCC1 = VCC2 = 5 V ±10%; 216 – 1 PRBS data at 100 Mbps | typ 1.4 ns | 19 |
| Propagation delay time tPLH, tPHL | VCC1 = VCC2 = 3.3 V ±10%; See Figure 6-1 | min 6 · typ 13.5 · max 18.5 ns | 20 |
| Pulse width distortion(1) |tPHL – tPLH| PWD | VCC1 = VCC2 = 3.3 V ±10%; See Figure 6-1 | max 5.9 ns | 20 |
| Channel-to-channel output skew time(2) tsk(o) | VCC1 = VCC2 = 3.3 V ±10%; Same-direction channels | max 4.4 ns | 20 |
| Part-to-part skew time(3) tsk(pp) | VCC1 = VCC2 = 3.3 V ±10% | max 5 ns | 20 |
| Output signal rise time tr | VCC1 = VCC2 = 3.3 V ±10%; See Figure 6-1 | typ 0.6 · max 3 ns | 20 |
| Output signal fall time tf | VCC1 = VCC2 = 3.3 V ±10%; See Figure 6-1 | typ 0.6 · max 3 ns | 20 |
| Disable propagation delay, high-to-high impedance output tPHZ | VCC1 = VCC2 = 3.3 V ±10%; See Figure 6-2 | typ 19 · max 31 ns | 20 |
| Disable propagation delay, low-to-high impedance output tPLZ | VCC1 = VCC2 = 3.3 V ±10%; See Figure 6-2 | typ 18 · max 30 ns | 20 |
| Enable propagation delay, high impedance-to-high output for ISO774x tPZH | VCC1 = VCC2 = 3.3 V ±10%; See Figure 6-2; without F suffix | typ 14 · max 30 ns | 20 |
| Enable propagation delay, high impedance-to-low output for ISO774x tPZL | VCC1 = VCC2 = 3.3 V ±10%; See Figure 6-2; without F suffix | typ 2.5 · max 8.5 us | 20 |
| Default output delay time from input power loss tDO | VCC1 = VCC2 = 3.3 V ±10%; Measured from the time VCC goes below 1.7V. See Figure 6-4 | typ 0.1 · max 0.3 us | 20 |
| Time interval error tie | VCC1 = VCC2 = 3.3 V ±10%; 216 – 1 PRBS data at 100 Mbps | typ 1.3 ns | 20 |
| Propagation delay time tPLH, tPHL | VCC1 = VCC2 = 2.5 V ±10%; See Figure 6-1 | min 7.5 · typ 14 · max 21 ns | 21 |
| Pulse width distortion(1) |tPHL – tPLH| PWD | VCC1 = VCC2 = 2.5 V ±10%; See Figure 6-1 | max 5.9 ns | 21 |
| Channel-to-channel output skew time(2) tsk(o) | VCC1 = VCC2 = 2.5 V ±10%; Same-direction channels | max 4.4 ns | 21 |
| Part-to-part skew time(3) tsk(pp) | VCC1 = VCC2 = 2.5 V ±10% | max 5.3 ns | 21 |
| Output signal rise time tr | VCC1 = VCC2 = 2.5 V ±10%; See Figure 6-1 | typ 0.8 · max 3.5 ns | 21 |
| Output signal fall time tf | VCC1 = VCC2 = 2.5 V ±10%; See Figure 6-1 | typ 0.8 · max 3.5 ns | 21 |
| Disable propagation delay, high-to-high impedance output tPHZ | VCC1 = VCC2 = 2.5 V ±10%; See Figure 6-2 | typ 24 · max 41 ns | 21 |
| Disable propagation delay, low-to-high impedance output tPLZ | VCC1 = VCC2 = 2.5 V ±10%; See Figure 6-2 | typ 22 · max 40 ns | 21 |
| Enable propagation delay, high impedance-to-high output for ISO774x tPZH | VCC1 = VCC2 = 2.5 V ±10%; See Figure 6-2; without F suffix | typ 18 · max 40 ns | 21 |
| Enable propagation delay, high impedance-to-low output for ISO774x tPZL | VCC1 = VCC2 = 2.5 V ±10%; See Figure 6-2; without F suffix | typ 2.7 · max 8.5 us | 21 |
| Default output delay time from input power loss tDO | VCC1 = VCC2 = 2.5 V ±10%; Measured from the time VCC goes below 1.7V. See Figure 6-4 | typ 0.1 · max 0.3 us | 21 |
| Time interval error tie | VCC1 = VCC2 = 2.5 V ±10%; 216 – 1 PRBS data at 100 Mbps | typ 1.5 ns | 21 |
Pins, by the datasheet
16- 1 VCC1
- Power supply, side 1. · p. 5
- 2 GND1
- Ground connection for VCC1. · p. 5
- 3 INA
- Input, channel A. · p. 5
- 4 INB
- Input, channel B. · p. 5
- 5 INC
- Input, channel C. · p. 5
- 6 OUTD
- Output, channel D. · p. 5
- 7 EN1
- Side 1 outputs are enabled when high or open and in high impedance when low. · p. 5
- 8 GND1
- Ground connection for VCC1. · p. 5
- 9 GND2
- Ground connection for VCC2. · p. 5
- 10 EN2
- Side 2 outputs are enabled when high or open and in high impedance when low. · p. 5
- 11 IND
- Input, channel D. · p. 5
- 12 OUTC
- Output, channel C. · p. 5
- 13 OUTB
- Output, channel B. · p. 5
- 14 OUTA
- Output, channel A. · p. 5
- 15 GND2
- Ground connection for VCC2. · p. 5
- 16 VCC2
- Power supply, side 2. · p. 5
Parameters
21- CMTI(kV/us)
- 100kV/us
- Current - Supply
- 6mA
- Current - Supply(Max)
- 39.4mA
- Data Rate(Max)
- 100Mbps
- Features
- Fail-safe output
- Isolation Voltage(Vrms)
- 5000
- Junction Temperature(Max)
- 150℃
- Number of Channels
- 4
- Number of Forward Channels
- 3
- Number of Reverse Channels
- 1
- Operating Temperature
- -55℃~+125℃
- Output Current per Pin(Max)
- 15mA
- Propagation Delay(tpd)
- 10.7ns
- Rise Time
- 600ps
- Thermal Resistance(Junction to Ambient)
- 83.4℃/W
- Thermal Resistance(Junction to Board)
- 48℃/W
- Thermal Resistance(Junction to Case)
- 46℃/W
- Voltage - Supply
- 2.25V~5.5V
- Voltage - Supply(Absolute Max)
- 6V
- Voltage - Supply(VCCA)
- 2.25V~5.5V
- Voltage - Supply(VCCB)
- 2.25V~5.5V
Order codes
1- ISO7741BDWRLCSC C2862696
Pinout
16| Pin | Name | Type |
|---|---|---|
| 1 | VCC1 | Unspecified |
| 2 | GND1 | Unspecified |
| 3 | INA | Unspecified |
| 4 | INB | Unspecified |
| 5 | INC | Unspecified |
| 6 | OUTD | Unspecified |
| 7 | EN1 | Unspecified |
| 8 | GND1 | Unspecified |
| 9 | GND2 | Unspecified |
| 10 | EN2 | Unspecified |
| 11 | IND | Unspecified |
| 12 | OUTC | Unspecified |
| 13 | OUTB | Unspecified |
| 14 | OUTA | Unspecified |
| 15 | GND2 | Unspecified |
| 16 | VCC2 | Unspecified |
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Is there a KiCad symbol and footprint for the ISO7741BDW?
Yes. The symbol is EasyEDA_Cloud:XISO6041HDFPR and the footprint Package_SO:SOIC-16W_7.5x10.3mm_P1.27mm, both drawn on this page. PCBKit places them on a board for you when you design with it.
What package is the ISO7741BDW?
SOIC-16-300mil, with 16 pins. Its footprint is drawn on this page.
Where is the ISO7741BDW datasheet?
Texas Instruments publishes it: the Datasheet link on this page opens it.
Where can I order the ISO7741BDW?
JLCPCB lists it as part C2862696, with 2,262 in stock; the sellers' links on this page open their listings.
What can replace the ISO7741BDW?
Parts like it in the library: the ISO7741DW by Texas Instruments, the SSP5840ED by Shanghai Siproin Microelectronics, the ISO7740DW by Texas Instruments and the ISO7760FDWR by Texas Instruments. Check their datasheets: a part that fits the footprint may still differ in its ratings.
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8
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