DAC5571IDBV
Texas InstrumentsExtended
-40℃~+105℃ 0.25LSB 1 125uA 2.7V~5.5V 7us 8 I2C Voltage Buffer SOT-23-6 Digital to Analog Converters (DAC) ROHS
- Part id
- ti/DAC5571IDBV
- Category
- Digital To Analog Converters (DAC)
- Package
- SOT-23-6
- Pins
- 6
- In stock
- 2,822 at JLCPCB (C24061)
Overview
The DAC5571IDBV is a digital To Analog Converter made by Texas Instruments in a SOT-23-6 package with 6 pins. -40℃~+105℃ 0.25LSB 1 125uA 2.7V~5.5V 7us 8 I2C Voltage Buffer SOT-23-6 Digital to Analog Converters (DAC) ROHS.
PCBKit's library has its KiCad symbol (Celestial_DAC:TI DAC5571I, from Altium's library) and its footprint (Package_TO_SOT_SMD:SOT-23-6, from KiCad's library), ready for a KiCad board. 2,822 are in stock at JLCPCB (part C24061).
Symbol
Footprint
From the datasheet
15- Supply, least
- 2.7 V · VDD, recommended operating min · p. 3
- Supply, most
- 5.5 V · VDD, recommended operating max · p. 3
- Supply, absolute maximum
- 6 V · VDD to GND, absolute max · p. 2
- Works from
- -40 °C · Operating temperature min · p. 2
- Works up to
- 105 °C · Operating temperature max · p. 2
- Junction, hottest
- 150 °C · Junction temperature max · p. 2
- Takes working
- 155 µA · VDD = +3.6 V to +5.5 V, DAC active excluding load, typical · p. 3
- Takes working
- 125 µA · VDD = +2.7 V to +3.6 V, DAC active excluding load, typical · p. 3
- Takes at most
- 200 µA · VDD = +3.6 V to +5.5 V, DAC active excluding load, max · p. 3
- Takes asleep
- 200 nA · VDD = +3.6 V to +5.5 V, all power-down modes, typical · p. 3
- Takes asleep
- 50 nA · VDD = +2.7 V to +3.6 V, all power-down modes, typical · p. 3
- Junction to air (SOT23-6)
- 240 K/W · Junction to ambient thermal impedance · p. 2
- Data rate, most
- 3.4 Mbit/s · I2C interface max · p. 1
- Takes working
- 150 µA · VDD typical operating current at 5 V · p. 17
- Takes working
- 120 µA · VDD typical operating current at 3 V · p. 17
What it is and has
13- DAC
- Single-channel, 8-bit · p. 1
- Update rate
- 188 KSPS · p. 1
- Power-on reset
- Zero output · p. 1
- Monotonicity
- Specified monotonic by design · p. 1
- I2C
- Up to 3.4 Mbps · p. 1
- Output amplifier
- On-chip output buffer amplifier · p. 1
- Input register
- Double-buffered · p. 1
- Address support
- Up to two DAC5571s · p. 1
- Package
- 6-lead SOT23 · p. 1
- Output voltage range
- 0 V to VDD · p. 1
- DAC
- Single-channel, 8-bit, buffered voltage output · p. 1
- Power-on reset
- Zero-code output until a valid write · p. 17
- I2C addressing
- 7-bit · p. 13
Around it
2- cap 0.1-µF
- between VDD and GND; Recommended supply bypass capacitor · p. 18
- cap 100-µF
- between VDD and GND; Electrolytic capacitor for additional supply bypassing when required · p. 18
Specifications
90| Parameter | Conditions | As printed | Page |
|---|---|---|---|
| VDD to GND | min -0.3 · max 6 V | 2 | |
| Digital input voltage to GND | Maximum +VDD+0.3 V | min -0.3 V | 2 |
| VOUT to GND | Maximum +VDD+0.3 V | min -0.3 V | 2 |
| Operating temperature range | min -40 · max 105 °C | 2 | |
| Storage temperature range | min -65 · max 150 °C | 2 | |
| Junction temperature range (TJ max) TJ | max 150 °C | 2 | |
| Thermal impedance, RΘJA RΘJA | SOT23-6 | max 240 °C/W | 2 |
| Lead temperature, soldering | Vapor phase (60s) | max 215 °C | 2 |
| Lead temperature, soldering | Infrared (15s) | max 220 °C | 2 |
| Resolution | min 8 Bits | 3 | |
| Relative accuracy | Linearity calculated using a reduced code range of 3 to 253; output unloaded. Maximum magnitude ±0.5 LSB. | max 0.5 LSB | 3 |
| Differential nonlinearity | Assured monotonic by design; maximum magnitude ±0.25 LSB | max 0.25 LSB | 3 |
| Zero code error | typ 5 · max 20 mV | 3 | |
| Full-scale error | All ones loaded to DAC register | typ -0.15 · max -1.25 % of FSR | 3 |
| Gain error | Maximum magnitude ±1.25% of FSR | max 1.25 % of FSR | 3 |
| Zero code error drift | Typical magnitude ±7 uV/°C | typ 7 uV/°C | 3 |
| Gain temperature coefficient | Typical magnitude ±3 ppm of FSR/°C | typ 3 ppm of FSR/°C | 3 |
| Output voltage range | Maximum VDD | min 0 V | 3 |
| Output voltage settling time | 1/4 Scale to 3/4 scale change (400H to C00H); RL= ∞ | typ 6 · max 8 us | 3 |
| Slew rate | typ 1 V/us | 3 | |
| Capacitive load stability | RL = ∞ | typ 470 pF | 3 |
| Capacitive load stability | RL = 2 kΩ | typ 1000 pF | 3 |
| Code change glitch impulse | 1 LSB Change around major carry | typ 20 nV-s | 3 |
| Digital feedthrough | typ 0.5 nV-s | 3 | |
| DC output impedance | typ 1 Ω | 3 | |
| Short-circuit current | VDD = +5 V | typ 50 mA | 3 |
| Short-circuit current | VDD = +3 V | typ 20 mA | 3 |
| Power-up time | Coming out of power-down mode, VDD = +5 V | typ 2.5 us | 3 |
| Power-up time | Coming out of power-down mode, VDD = +3 V | typ 5 us | 3 |
| Input current | Maximum magnitude ±1 uA | max 1 uA | 3 |
| Pin capacitance | max 3 pF | 3 | |
| VDD VDD | min 2.7 · max 5.5 V | 3 | |
| IDD (normal operation) IDD | DAC active and excluding load current; VDD = +3.6 V to +5.5 V; VIH = VDD and VIL = GND | typ 155 · max 200 uA | 3 |
| IDD (normal operation) IDD | DAC active and excluding load current; VDD = +2.7 V to +3.6 V; VIH = VDD and VIL = GND | typ 125 · max 160 uA | 3 |
| IDD (all power-down modes) IDD | VDD = +3.6 V to +5.5 V; VIH = VDD and VIL = GND | typ 0.2 · max 1 uA | 3 |
| IDD (all power-down modes) IDD | VDD = +2.7 V to +3.6 V; VIH = VDD and VIL = GND | typ 0.05 · max 1 uA | 3 |
| IOUT/IDD IOUT/IDD | ILOAD = 2 mA, VDD = +5 V | typ 93 % | 3 |
| SCL Clock Frequency fSCL | Standard mode | max 100 kHz | 4 |
| SCL Clock Frequency fSCL | Fast mode | max 400 kHz | 4 |
| SCL Clock Frequency fSCL | High-speed mode, CB - 100 pF max | max 3.4 MHz | 4 |
| SCL Clock Frequency fSCL | High-Speed mode, CB - 400 pF max | max 1.7 MHz | 4 |
| Bus Free Time Between a STOP and START Condition tBUF | Standard mode | min 4.7 us | 4 |
| Bus Free Time Between a STOP and START Condition tBUF | Fast mode | min 1.3 us | 4 |
| Hold Time (Repeated) START Condition tHD; tSTA | Standard mode | min 4 us | 4 |
| Hold Time (Repeated) START Condition tHD; tSTA | Fast mode | min 600 ns | 4 |
| Hold Time (Repeated) START Condition tHD; tSTA | High-speed mode | min 160 ns | 4 |
| LOW Period of the SCL Clock tLOW | Standard mode | min 4.7 us | 4 |
| LOW Period of the SCL Clock tLOW | Fast mode | min 1.3 us | 4 |
| LOW Period of the SCL Clock tLOW | High-speed mode, CB - 100 pF max | min 160 ns | 4 |
| LOW Period of the SCL Clock tLOW | High-speed mode, CB - 400 pF max | min 320 ns | 4 |
| HIGH Period of the SCL Clock tHIGH | Standard mode | min 4 us | 4 |
| HIGH Period of the SCL Clock tHIGH | Fast mode | min 600 ns | 4 |
| HIGH Period of the SCL Clock tHIGH | High-speed mode, CB - 100 pF max | min 60 ns | 4 |
| HIGH Period of the SCL Clock tHIGH | High-speed mode, CB - 400 pF max | min 120 ns | 4 |
| Setup Time for a Repeated START Condition tSU; tSTA | Standard mode | min 4.7 us | 4 |
| Setup Time for a Repeated START Condition tSU; tSTA | Fast mode | min 600 ns | 4 |
| Setup Time for a Repeated START Condition tSU; tSTA | High-speed mode | min 160 ns | 4 |
| Data Setup Time tSU; tDAT | Standard mode | min 250 ns | 4 |
| Data Setup Time tSU; tDAT | Fast mode | min 100 ns | 4 |
| Data Setup Time tSU; tDAT | High-speed mode | min 10 ns | 4 |
| Data Hold Time tHD; tDAT | Standard mode | min 0 · max 3.45 us | 4 |
| Data Hold Time tHD; tDAT | Fast mode | min 0 · max 0.9 us | 4 |
| Data Hold Time tHD; tDAT | High-speed mode, CB - 100 pF max | min 0 · max 70 ns | 4 |
| Data Hold Time tHD; tDAT | High-speed mode, CB - 400 pF max | min 0 · max 150 ns | 4 |
| Rise Time of SCL Signal tRCL | Standard mode | max 1000 ns | 4 |
| Rise Time of SCL Signal tRCL | Fast mode; minimum 20 + 0.1CB | max 300 ns | 4 |
| Rise Time of SCL Signal tRCL | High-speed mode, CB - 100 pF max | min 10 · max 40 ns | 4 |
| Rise Time of SCL Signal tRCL | High-speed mode, CB - 400 pF max | min 20 · max 80 ns | 4 |
| Rise Time of SCL Signal After a Repeated START Condition and After an Acknowledge BIT tRCL1 | Standard mode | max 1000 ns | 4 |
| Rise Time of SCL Signal After a Repeated START Condition and After an Acknowledge BIT tRCL1 | Fast mode; minimum 20 + 0.1CB | max 300 ns | 4 |
| Rise Time of SCL Signal After a Repeated START Condition and After an Acknowledge BIT tRCL1 | High-speed mode, CB - 100 pF max | min 10 · max 80 ns | 4 |
| Rise Time of SCL Signal After a Repeated START Condition and After an Acknowledge BIT tRCL1 | High-speed mode, CB - 400 pF max | min 20 · max 160 ns | 4 |
| Fall Time of SCL Signal tFCL | Standard mode | max 300 ns | 4 |
| Fall Time of SCL Signal tFCL | Fast mode; minimum 20 + 0.1CB | max 300 ns | 4 |
| Fall Time of SCL Signal tFCL | High-speed mode, CB - 100 pF max | min 10 · max 40 ns | 4 |
| Fall Time of SCL Signal tFCL | High-speed mode, CB - 400 pF max | min 20 · max 80 ns | 4 |
| Rise Time of SDA Signal tRDA | Standard mode | max 1000 ns | 4 |
| Rise Time of SDA Signal tRDA | Fast mode; minimum 20 + 0.1CB | max 300 ns | 4 |
| Rise Time of SDA Signal tRDA | High-speed mode, CB - 100 pF max | min 10 · max 80 ns | 4 |
| Rise Time of SDA Signal tRDA | High-speed mode, CB - 400 pF max | min 20 · max 160 ns | 4 |
| Fall Time of SDA Signal tFDA | Standard mode | max 300 ns | 4 |
| Fall Time of SDA Signal tFDA | Fast mode; minimum 20 + 0.1CB | max 300 ns | 4 |
| Fall Time of SDA Signal tFDA | High-speed mode, CB - 100 pF max | min 10 · max 80 ns | 4 |
| Fall Time of SDA Signal tFDA | High-speed mode, CB - 400 pF max | min 20 · max 160 ns | 4 |
| Setup Time for STOP Condition tSU; tSTO | Standard mode | min 4 us | 5 |
| Setup Time for STOP Condition tSU; tSTO | Fast mode | min 600 ns | 5 |
| Setup Time for STOP Condition tSU; tSTO | High-speed mode | min 160 ns | 5 |
| Capacitive Load for SDA and SCL CB | max 400 pF | 5 | |
| Pulse Width of Spike Suppressed tSP | Fast mode | max 50 ns | 5 |
| Pulse Width of Spike Suppressed tSP | High-speed mode | max 10 ns | 5 |
Pins, by the datasheet
6- 1 VOUT
- Analog output voltage from DAC. · p. 2
- 2 GND
- Ground reference point for all circuitry. · p. 2
- 3 VDD
- Analog Voltage Supply Input. · p. 2
- 4 SDA
- Serial Data Input. · p. 2
- 5 SCL
- Serial Clock Input. · p. 2
- 6 A0
- Device Address Select. · p. 2
Ordering codes, by the datasheet
6- DAC5571IDBVT
- SOT23-6 · 250-Piece Small Tape and Reel; –40°C to +105°C · p. 2
- DAC5571IDBVR
- SOT23-6 · 3000-Piece Tape and Reel; –40°C to +105°C · p. 2
- DAC5571IDBVR.B
- SOT-23 (DBV) · 6 pins; 3000, LARGE T&R; operating temperature -40 to 105 °C · p. 19
- DAC5571IDBVRG4
- SOT-23 (DBV) · 6 pins; 3000, LARGE T&R; operating temperature -40 to 105 °C · p. 19
- DAC5571IDBVT.B
- SOT-23 (DBV) · 6 pins; 250, SMALL T&R; operating temperature -40 to 105 °C · p. 19
- DAC5571IDBVTG4
- SOT-23 (DBV) · 6 pins; 250, SMALL T&R; operating temperature -40 to 105 °C · p. 19
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Questions
Is there a KiCad symbol and footprint for the DAC5571IDBV?
Yes. The symbol is Celestial_DAC:TI DAC5571I and the footprint Package_TO_SOT_SMD:SOT-23-6, both drawn on this page. PCBKit places them on a board for you when you design with it.
What package is the DAC5571IDBV?
SOT-23-6, with 6 pins. Its footprint is drawn on this page.
Where is the DAC5571IDBV datasheet?
Texas Instruments publishes it: the Datasheet link on this page opens it.
Where can I order the DAC5571IDBV?
JLCPCB lists it as part C24061, with 2,822 in stock; the sellers' links on this page open their listings.
What can replace the DAC5571IDBV?
Parts like it in the library: the MCP4725A0-E/CH by Microchip Technology, the MCP4726A0-E/CH by Microchip Technology, the MCP4716A0-E/CH by Microchip Technology and the HT7512ARTZ by HTCSEMI. Check their datasheets: a part that fits the footprint may still differ in its ratings.