ADS1256IDB

Q: Is there a KiCad symbol and footprint for the ADS1256IDB?

Yes. The symbol is Celestial_ADC:TI ADS1256 and the footprint Package_SO:SSOP-28_5.3x10.2mm_P0.65mm, both drawn on this page. PCBKit places them on a board for you when you design with it.

Q: What package is the ADS1256IDB?

SSOP-28-208mil, with 28 pins. Its footprint is drawn on this page.

Q: Where is the ADS1256IDB datasheet?

Texas Instruments publishes it: the Datasheet link on this page opens it.

Q: Where can I order the ADS1256IDB?

JLCPCB lists it as part C28186, with 4,577 in stock; the sellers' links on this page open their listings.

Q: What can replace the ADS1256IDB?

Parts like it in the library: the ADS1255IDB by Texas Instruments. Check their datasheets: a part that fits the footprint may still differ in its ratings.

Q: Which open-source boards use the ADS1256IDB?

1 board in 1 repository on GitHub; the most starred are listed on this page, with their KiCad files.

Texas InstrumentsExtended

-40℃~+105℃ 1.8V~3.6V、5V 24 2uA 30kHz 30kHz 4 5V 7.68MHz External External SPI Sigma-Delta Support Yes SSOP-28-208mil Analog to Digital Converters (ADC) ROHS

Datasheet JLCPCB LCSC

Part id: ti/ADS1256IDB
Category: Analog To Digital Converters (ADCs)
Package: SSOP-28-208mil
Pins: 28
In stock: 4,577 at JLCPCB (C28186)
Used on: 1 open-source board

Overview

The ADS1256IDB is an analog To Digital Converter made by Texas Instruments in a SSOP-28-208mil package with 28 pins. -40℃~+105℃ 1.8V~3.6V、5V 24 2uA 30kHz 30kHz 4 5V 7.68MHz External External SPI Sigma-Delta Support Yes SSOP-28-208mil Analog to Digital Converters (ADC) ROHS.

PCBKit's library has its KiCad symbol (Celestial_ADC:TI ADS1256, from Altium's library) and its footprint (Package_SO:SSOP-28_5.3x10.2mm_P0.65mm, from KiCad's library), ready for a KiCad board. 4,577 are in stock at JLCPCB (part C28186). 1 open-source board in 1 repository on GitHub use it.

Symbol

Celestial_ADC:TI ADS1256From Altium's library

Footprint

Package_SO:SSOP-28_5.3x10.2mm_P0.65mmFrom KiCad's library

From the datasheet

Supply, least: 4.75 V · AVDD, recommended operating min · p. 4
Supply, most: 5.25 V · AVDD, recommended operating max · p. 4
Supply, least: 1.8 V · DVDD, recommended operating min · p. 4
Supply, most: 3.6 V · DVDD, recommended operating max · p. 4
Supply, absolute maximum: 6 V · AVDD to AGND, absolute max · p. 2
Supply, absolute maximum: 3.6 V · DVDD to DGND, absolute max · p. 2
Works from: -40 °C · Operating temperature min · p. 4
Works up to: 105 °C · Operating temperature max · p. 4
Junction, hottest: 150 °C · Junction temperature absolute max · p. 2
Takes working: 7.9 mA · sum of AVDD and DVDD typical normal currents, PGA = 1, buffer off, CLKOUT off, DVDD = 3.3 V · p. 4
Takes at most: 52 mA · sum of AVDD and DVDD max normal currents, PGA = 64, buffer on, CLKOUT off, DVDD = 3.3 V · p. 4
Takes asleep: 115 µA · sum of AVDD and DVDD typical standby currents, CLKOUT off, DVDD = 3.3 V · p. 4
Takes asleep: 4 µA · sum of AVDD and DVDD max power-down currents · p. 4
Works up to: 85 °C · Operating temperature max, ADS1256IDBR · p. 39

What it is and has

Resolution: 24 bits, no missing codes at all data rates and PGA settings · p. 3
Data output rate: 2.5 to 30,000 SPS at fCLKIN = 7.68MHz · p. 3
Programmable gain amplifier: Gain 1 to 64 · p. 3
Differential inputs: 4 · p. 1
Single-ended inputs: 8 · p. 1
Digital I/O: 4; D0 also provides clock output · p. 5
Input buffer: Chopper-stabilized · p. 1
Serial interface: 5V tolerant, SPI-compatible · p. 1
Resolution: 24 bits, no missing codes · p. 1
Noise-free resolution: Up to 23 bits · p. 1

Specifications

Parameter	Conditions	As printed	Page
AVDD to AGND	Over operating free-air temperature range	min -0.3 · max 6 V	2
DVDD to DGND	Over operating free-air temperature range	min -0.3 · max 3.6 V	2
AGND to DGND	Over operating free-air temperature range	min -0.3 · max 0.3 V	2
Input Current	Momentary	max 100 mA	2
Input Current	Continuous	max 10 mA	2
Analog inputs to AGND	Maximum: AVDD + 0.3 V	min -0.3 V	2
Digital inputs	DIN, SCLK, CS, RESET, SYNC/PDWN, XTAL1/CLKIN to DGND	min -0.3 · max 6 V	2
Digital inputs	D0/CLKOUT, D1, D2, D3 to DGND; maximum: DVDD + 0.3 V	min -0.3 V	2
Maximum Junction Temperature		max 150 °C	2
Operating Temperature Range		min -40 · max 105 °C	2
Storage Temperature Range		min -60 · max 150 °C	2
Lead Temperature (soldering, 10s)	Soldering, 10s	max 300 °C	2
Programmable gain amplifier		min 1 · max 64	3
Differential input impedance	Buffer off, PGA = 32, 64	typ 4.7 kΩ	3
Differential input impedance	Buffer on, fDATA ≤ 50Hz(1)	typ 80 MΩ	3
Sensor detect current sources	SDCS[1:0] = 01	typ 0.5 uA	3
Sensor detect current sources	SDCS[1:0] = 10	typ 2 uA	3
Sensor detect current sources	SDCS[1:0] = 11	typ 10 uA	3
Resolution		min 24 Bit	3
No missing codes	All data rates and PGA settings	min 24 Bit	3
Data rate (fDATA) fDATA	fCLKIN = 7.68MHz	min 2.5 · max 30000 SPS(2)	3
Integral nonlinearity	Differential input, PGA = 1; values are ±	typ 0.0003 · max 0.001 %FSR(3)	3
Integral nonlinearity	Differential input, PGA = 64; typical is ±	typ 0.0007 %FSR	3
Offset drift	PGA = 1; typical is ±	typ 100 nV/°C	3
Offset drift	PGA = 64; typical is ±	typ 4 nV/°C	3
Gain error	After calibration, PGA = 1, Buffer on; typical is ±	typ 0.005 %	3
Gain error	After calibration, PGA = 64, Buffer on; typical is ±	typ 0.03 %	3
Gain drift	PGA = 1; typical is ±	typ 0.8 ppm/°C	3
Gain drift	PGA = 64; typical is ±	typ 0.8 ppm/°C	3
Common-mode rejection	fCM(4) = 60Hz, fDATA = 30kSPS(5)	min 95 · typ 110 dB	3
AVDD power-supply rejection	±5% Δ in AVDD	min 60 · typ 70 dB	3
DVDD power-supply rejection	±10% Δ in DVDD	typ 100 dB	3
Reference input voltage (VREF) VREF	VREF ≡ VREFP − VREFN	min 0.5 · typ 2.5 · max 2.6 V	3
Voltage reference impedance	fCLKIN = 7.68MHz	typ 18.5 kΩ	3
VIH VIH	DIN, SCLK, XTAL1/CLKIN, SYNC/PDWN, CS, RESET; minimum: 0.8 DVDD	max 5.25 V	3
Input hysteresis		typ 0.5 V	3
Input leakage	0 < VDIGITAL INPUT < DVDD; maximum is ±	max 10 uA	3
Master clock rate	External crystal between XTAL1 and XTAL2	min 2 · typ 7.68 · max 10 MHz	3
Master clock rate	External oscillator driving CLKIN	min 0.1 · typ 7.68 · max 10 MHz	3
AVDD AVDD		min 4.75 · max 5.25 V	4
DVDD DVDD		min 1.8 · max 3.6 V	4
AVDD current	Power-down mode	max 2 uA	4
AVDD current	Standby mode	typ 20 uA	4
AVDD current	Normal mode, PGA = 1, Buffer off	typ 7 · max 10 mA	4
AVDD current	Normal mode, PGA = 64, Buffer off	typ 16 · max 22 mA	4
AVDD current	Normal mode, PGA = 1, Buffer on	typ 13 · max 19 mA	4
AVDD current	Normal mode, PGA = 64, Buffer on	typ 36 · max 50 mA	4
DVDD current	Power-down mode	max 2 uA	4
DVDD current	Standby mode, CLKOUT off, DVDD = 3.3V	typ 95 uA	4
DVDD current	Normal mode, CLKOUT off, DVDD = 3.3V	typ 0.9 · max 2 mA	4
Power dissipation	Normal mode, PGA = 1, Buffer off, DVDD = 3.3V	typ 38 · max 57 mW	4
Power dissipation	Standby mode, DVDD = 3.3V	typ 0.4 mW	4
Specified	Temperature Range	min -40 · max 85 °C	4
Operating	Temperature Range	min -40 · max 105 °C	4
Storage	Temperature Range	min -60 · max 150 °C	4
SCLK period t1	Minimum in master clock periods	min 4 τCLKIN(1)	6
SCLK period t1	Maximum in output data periods	max 10 τDATA(2)	6
SCLK pulse width: high t2H	Minimum	min 200 ns	6
SCLK pulse width: high t2H	Maximum in output data periods	max 9 τDATA	6
SCLK pulse width: low t2L		min 200 ns	6
CS low to first SCLK: setup time(3) t3		min 0 ns	6
Valid DIN to SCLK falling edge: setup time t4		min 50 ns	6
Valid DIN to SCLK falling edge: hold time t5		min 50 ns	6
Delay from last SCLK edge for DIN to first SCLK rising edge for DOUT: RDATA, RDATAC, RREG Commands t6		min 50 τCLKIN	6
SCLK rising edge to valid new DOUT: propagation delay(4) t7	DOUT load = 20pF ⎥⎥ 100kΩ to DGND	max 50 ns	6
SCLK rising edge to DOUT invalid: hold time t8		min 0 ns	6
Last SCLK falling edge to DOUT high impedance t9	DOUT goes high impedance immediately when CS goes high	min 6 · max 10 τCLKIN	6
CS low after final SCLK falling edge t10		min 8 τCLKIN	6
Final SCLK falling edge of command to first SCLK rising edge of next command. t11	RREG, WREG, RDATA	min 4 τCLKIN	6
Final SCLK falling edge of command to first SCLK rising edge of next command. t11	RDATAC, SYNC	min 24 τCLKIN	6
SCLK reset pattern, first high pulse t12		min 300 · max 500 τCLKIN(1)	7
SCLK reset pattern, low pulse t13		min 5 τCLKIN	7
SCLK reset pattern, second high pulse t14		min 550 · max 750 τCLKIN	7
SCLK reset pattern, third high pulse t15		min 1050 · max 1250 τCLKIN	7
RESET, SYNC/PDWN, pulse width t16		min 4 τCLKIN(1)	7
SYNC/PDWN rising edge to CLKIN rising edge t16B		min -25 · max 25 ns	7
Conversion data invalid while being updated (DRDY shown with no data retrieval) t17		min 16 τCLKIN(1)	7
ZeffA ZeffA	PGA setting = 1; fCLKIN = 7.68MHz	typ 260 kΩ	17
ZeffB ZeffB	PGA setting = 1; fCLKIN = 7.68MHz	typ 220 kΩ	17
ZeffA ZeffA	PGA setting = 2; fCLKIN = 7.68MHz	typ 130 kΩ	17
ZeffB ZeffB	PGA setting = 2; fCLKIN = 7.68MHz	typ 110 kΩ	17
ZeffA ZeffA	PGA setting = 4; fCLKIN = 7.68MHz	typ 65 kΩ	17
ZeffB ZeffB	PGA setting = 4; fCLKIN = 7.68MHz	typ 55 kΩ	17
ZeffA ZeffA	PGA setting = 8; fCLKIN = 7.68MHz	typ 33 kΩ	17
ZeffB ZeffB	PGA setting = 8; fCLKIN = 7.68MHz	typ 28 kΩ	17
ZeffA ZeffA	PGA setting = 16; fCLKIN = 7.68MHz	typ 16 kΩ	17
ZeffB ZeffB	PGA setting = 16; fCLKIN = 7.68MHz	typ 14 kΩ	17
ZeffA ZeffA	PGA setting = 32; fCLKIN = 7.68MHz	typ 8 kΩ	17
ZeffB ZeffB	PGA setting = 32; fCLKIN = 7.68MHz	typ 7 kΩ	17
ZeffA ZeffA	PGA setting = 64; fCLKIN = 7.68MHz	typ 8 kΩ	17
ZeffB ZeffB	PGA setting = 64; fCLKIN = 7.68MHz	typ 7 kΩ	17

Pins, by the datasheet

1 AVDD: Analog power supply. · p. 5
2 AGND: Analog ground. · p. 5
3 VREFN: Negative reference input. · p. 5
4 VREFP: Positive reference input. · p. 5
5 AINCOM: Analog input common. · p. 5
6 AIN0: Analog input 0. · p. 5
7 AIN1: Analog input 1. · p. 5
8 AIN2: Analog input 2. · p. 5
9 AIN3: Analog input 3. · p. 5
10 AIN4: Analog input 4. · p. 5
11 AIN5: Analog input 5. · p. 5
12 AIN6: Analog input 6. · p. 5
13 AIN7: Analog input 7. · p. 5
14 SYNC/PDWN: Active-low synchronization / power down input; Schmitt-trigger and 5V tolerant. · p. 5
15 RESET: Active-low reset input; Schmitt-trigger and 5V tolerant. · p. 5
16 DVDD: Digital power supply. · p. 5
17 DGND: Digital ground. · p. 5
18 XTAL2: Crystal oscillator connection; leave disconnected if an external clock is applied to XTAL1/CLKIN. · p. 5
19 XTAL1/CLKIN: Crystal oscillator connection / external clock input; 5V tolerant. · p. 5
20 CS: Active-low chip select; Schmitt-trigger and 5V tolerant. · p. 5
21 DRDY: Active-low data ready output. · p. 5
22 DOUT: Serial data output. · p. 5
23 DIN: Serial data input; Schmitt-trigger and 5V tolerant. · p. 5
24 SCLK: Serial clock input; Schmitt-trigger and 5V tolerant. · p. 5
25 D0/CLKOUT: Digital I/O 0 / clock output; Schmitt-trigger when configured as input. · p. 5
26 D1: Digital I/O 1; Schmitt-trigger when configured as input. · p. 5
27 D2: Digital I/O 2; Schmitt-trigger when configured as input. · p. 5
28 D3: Digital I/O 3; Schmitt-trigger when configured as input. · p. 5

Ordering codes, by the datasheet

ADS1256IDBR: SSOP, DB, 28 pins · Package quantity 1000; operating temperature -40 to 85 °C · p. 39
ADS1256IDBRG4: SSOP, DB, 28 pins · Package quantity 1000; operating temperature -40 to 85 °C · p. 39
ADS1256IDBT: SSOP, DB, 28 pins · Package quantity 250; operating temperature -40 to 85 °C · p. 39
ADS1256IDBTG4: SSOP, DB, 28 pins · Package quantity 250; operating temperature -40 to 85 °C · p. 39

Parameters

ADC architecture: Sigma-Delta
Clock Frequency: 7.68MHz
Clock/Oscillator: External
Current - Supply: 7.9mA
Current - Supply(Max): 52mA
Features: Built-in digital filter
Interface: SPI
Junction Temperature(Max): 150℃
Operating Temperature: -40℃~+105℃
Programmable Gain: Support
Quiescent Current (Iq): 2uA
Resolution (Bits): 24
Sampling Rate: 30kHz
Standby Current: 115uA
Voltage - Supply: 1.8V~5.25V
Voltage - Supply(Absolute Max): 6V
Voltage Reference: External
differential input: Yes
number of channels: 4

Order codes

ADS1256IDBTG4LCSC C1543590
ADS1256IDBRG4LCSC C2670656
ADS1256IDBRLCSC C28186
ADS1256IDBTLCSC C701629

Pinout

The pins of the ADS1256IDB
Pin	Name	Type
1	AVDD	Passive
2	AGND	Passive
3	VREFN	Passive
4	VREFP	Passive
5	AINCOM	Passive
6	AIN0	Passive
7	AIN1	Passive
8	AIN2	Passive
9	AIN3	Passive
10	AIN4	Passive
11	AIN5	Passive
12	AIN6	Passive
13	AIN7	Passive
14	SYNC/PDWN	Passive
15	RESET	Passive
16	DVDD	Passive
17	DGND	Passive
18	XTAL2	Passive
19	XTAL1/CLKIN	Passive
20	CS	Passive
21	DRDY	Passive
22	DOUT	Passive
23	DIN	Passive
24	SCLK	Passive
25	D0/CLKOUT	Passive
26	D1	Passive
27	D2	Passive
28	D3	Passive

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Parts like it

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Questions

Is there a KiCad symbol and footprint for the ADS1256IDB?