
STSPIN32G4
STMicroelectronicsExtended
-40℃~+125℃ 1A 3 5.5V~15V I2C、SPI、UART、CAN No Three Phase VFQFPN-64(9x9) Brushless DC (BLDC) Motor Driver ROHS
- Part id
- st/STSPIN32G4
- Category
- Intelligent Power Modules (IPM)
- Package
- VFQFPN-64(9x9)
- Pins
- 65
- In stock
- 210 at JLCPCB (C7434864)
- Used on
- 20 open-source boards
Overview
The STSPIN32G4 is an intelligent Power Module made by STMicroelectronics in a VFQFPN-64(9x9) package with 65 pins. -40℃~+125℃ 1A 3 5.5V~15V I2C、SPI、UART、CAN No Three Phase VFQFPN-64(9x9) Brushless DC (BLDC) Motor Driver ROHS.
PCBKit's library has its KiCad symbol (EasyEDA_Cloud:STSPIN32G4, from EasyEDA) and its footprint (EasyEDA_Cloud:VFQFPN-64_L9.0-W9.0-P0.50-TL-EP4.0, from EasyEDA), ready for a KiCad board. 210 are in stock at JLCPCB (part C7434864). 20 open-source boards in 16 repositories on GitHub use it.
Symbol
Footprint
From the datasheet
26- Supply, least
- 5.5 V · VM, recommended operating minimum · p. 6
- Supply, most
- 75 V · VM, recommended operating maximum · p. 6
- Supply, absolute maximum
- 78 V · VM, absolute maximum · p. 5
- Supply, most
- 15 V · VCC, externally provided maximum · p. 6
- Supply, absolute maximum
- 20 V · VCC, absolute maximum · p. 5
- Supply, least
- 3.3 V · REGIN, recommended operating minimum · p. 6
- Supply, absolute maximum
- 3.6 V · REG3V3, absolute maximum · p. 5
- Supply, least
- 1.62 V · VDDA, minimum with ADC or COMP used · p. 6
- Supply, most
- 3.6 V · VDDA, maximum with ADC or COMP used · p. 6
- Supply, least
- 1.71 V · VDDA, minimum with DAC used · p. 6
- Supply, least
- 2 V · VDDA, minimum with op-amp used · p. 6
- Supply, least
- 2.4 V · VDDA, minimum with VREFBUS used · p. 6
- Supply, least
- 1.55 V · VBAT, recommended operating minimum · p. 6
- Supply, absolute maximum
- 4 V · VDD, VDDA, VBAT, absolute maximum · p. 5
- Works from
- -40 °C · Operative ambient temperature minimum · p. 6
- Works up to
- 125 °C · Operative ambient temperature maximum, thermally limited · p. 6
- Junction, hottest
- 150 °C · Junction temperature absolute maximum · p. 5
- A pin gives at most
- 20 mA · MCU I/O source or sink absolute maximum · p. 5
- Gives
- 200 mA · VCC buck output maximum, thermally limited · p. 6
- Gives
- 150 mA · 3.3 V LDO output maximum, thermally limited · p. 6
- Output
- 3.3 V · 3.3 V LDO output typical, REGIN = 5 V, 150 mA · p. 9
- Current limit
- 1.2 A · Buck converter overcurrent threshold typical · p. 9
- Current limit
- 151 mA · 3.3 V LDO current limit minimum, REG3V3 shorted · p. 9
- Switches at
- 500 kHz · VCC buck switching frequency typical · p. 8
- Takes asleep
- 15 µA · VM standby typical at 75 V, standby regulator enabled, MCU excluded · p. 10
- Data rate, most
- 1 Mbit/s · I2C speed maximum · p. 10
What it is and has
29- Motor controller
- High performance 3-phase motor controller with embedded STM32G4 MCU · p. 1
- Motor supply voltage
- 5.5 V to 75 V · p. 1
- Gate drive capability
- 1 A sink/source · p. 1
- VDS protection
- VDS monitoring of the power stage MOSFETs · p. 1
- Bootstrap diodes
- Integrated · p. 1
- Driver configuration
- I2C accessible configuration and status registers · p. 1
- Cross-conduction protection
- Cross-conduction prevention · p. 1
- Microcontroller core
- STM32G431, 32-bit ARM Cortex-M4 MCU+FPU · p. 1
- Clock
- Up to 170 MHz · p. 1
- CORDIC
- Mathematical hardware accelerator for trigonometric functions · p. 1
- Flash memory
- 128 kB with proprietary code readout protection (PCROP) · p. 1
- OTP memory
- 1 kB · p. 1
- SRAM
- 32 kB with HW parity check · p. 1
- Motor control timers
- 2, 16-bit with up to 6 PWM channels · p. 1
- General purpose timers
- 8 · p. 1
- ADC
- 2, 12-bit, up to 19 channels, 4 Msps · p. 1
- DAC
- 4 channels, 12-bit · p. 1
- Comparators
- 4 ultra-fast rail-to-rail · p. 1
- Operational amplifiers
- 3 rail-to-rail, also usable in PGA mode · p. 1
- Voltage reference
- Internal high precision · p. 1
- GPIO
- Up to 40 · p. 1
- Interfaces
- I2C, SPI, UART and CAN · p. 1
- VCC buck converter
- Up to 200 mA, programmable output · p. 1
- LDO
- 3.3 V, up to 150 mA · p. 1
- Standby regulator
- Low quiescent linear regulator for MCU supply · p. 1
- Motor control
- Possibility to control 2 motors simultaneously from the same MCU · p. 1
- Standby
- Reduced power consumption · p. 1
- Debug
- SWD or JTAG · p. 1
- Temperature range
- -40 to +125°C · p. 1
Specifications
114| Parameter | Conditions | As printed | Page |
|---|---|---|---|
| Motor supply voltage VM | min -0.3 · max 78 V | 5 | |
| Gate driving supply voltage VCC | min -0.3 · max 20 V | 5 | |
| SW pin voltage VSW | Maximum: VM | min -2 V | 5 |
| 3.3 V LDO linear regulator input VREGIN | min -0.3 · max 20 V | 5 | |
| Logic supply voltage VREG3V3 | min -0.3 · max 3.6 V | 5 | |
| 3.3 V linear regulator voltage drop VREG3V3,drop | VREGIN - VREG3V3 | min -0.3 · max 20 V | 5 |
| 3.3 V LDO linear regulator power dissipation Pd,REG3V3 | max 1 W | 5 | |
| OUTx pins voltage VOUTx | Maximum: VM + 2 | min -2 V | 5 |
| Bootstrap pins voltage VBOOTx | min -0.3 · max 98 V | 5 | |
| High-side driver supply voltage VBOx | VBOOTx – VOUTx | min -0.3 · max 20 V | 5 |
| Low-side gates voltage VGLSx | -0.3 to VCC+0.3 | min -0.3 V | 5 |
| Output slew rate dVOUT/dt | ± 20 | min -20 · max 20 V/ns | 5 |
| SCREF input VSCREF | min -0.3 · max 3.6 V | 5 | |
| MCU main supply voltages(1) VDD, VDDA, VBAT | min -0.3 · max 4 V | 5 | |
| MCU logic input voltage (1) (2) VIO | FT_c pins; minimum VSS-0.3 | max 5.5 V | 5 |
| MCU logic input voltage (1) (2) VIO | TT_xx pins and other pins; minimum VSS-0.3 | max 4 V | 5 |
| MCU I/O output current(1) IIO | min -20 · max 20 mA | 5 | |
| MCU I/O total output current(1) (4) ∑IIO | min -100 · max 100 mA | 5 | |
| Storage temperature TSTG | min -55 · max 150 °C | 5 | |
| Junction temperature TJ | min -40 · max 150 °C | 5 | |
| Supply voltage VM | Actual operative range can be limited by UVLO protections. | min 5.5 · max 75 V | 6 |
| Supply voltage slope dVM /dt | max 10 V/ us | 6 | |
| VCC Buck converter output and gate driving supply voltage VCC | Internally generated, set to 8 V | typ 8 V | 6 |
| VCC Buck converter output and gate driving supply voltage VCC | Internally generated, set to 10 V | typ 10 V | 6 |
| VCC Buck converter output and gate driving supply voltage VCC | Internally generated, set to 12 V | typ 12 V | 6 |
| VCC Buck converter output and gate driving supply voltage VCC | Internally generated, set to 15 V | typ 15 V | 6 |
| VCC Buck converter output and gate driving supply voltage VCC | Externally provided; actual operative range can be limited by UVLO protections. | min 5.5 · max 15 V | 6 |
| VCC Buck converter output current ICC | Actual operative range can be limited by thermal shutdown. | max 200 mA | 6 |
| 3.3 V LDO linear regulator input VREGIN | min 3.3 · max 15 V | 6 | |
| Logic supply voltage VREG3V3 | typ 3.3 V | 6 | |
| 3.3 V linear regulator output current IREG3V3 | Actual operative range can be limited by thermal shutdown. | max 150 mA | 6 |
| Standby regulator output current IREG3V3,Stby | VM ≥ 8V | max 6 mA | 6 |
| SCREF input VSCREF | Protection enabled | min 0.2 · max 2.5 V | 6 |
| SCREF input VSCREF | Protection disabled | min 2.9 · max 3.3 V | 6 |
| MCU analog supply voltage VDDA | ADC or COMP used | min 1.62 · max 3.6 V | 6 |
| MCU analog supply voltage VDDA | DAC 1 MSPS or DAC 15 MSPS | min 1.71 · max 3.6 V | 6 |
| MCU analog supply voltage VDDA | Op-amp used | min 2 · max 3.6 V | 6 |
| MCU analog supply voltage VDDA | VREFBUS used | min 2.4 · max 3.6 V | 6 |
| MCU analog supply voltage VDDA | ADC, DAC, Op-amp, COMP, VREFBUF not used | min 0 · max 3.6 V | 6 |
| MCU backup operating voltage VBAT | min 1.55 · max 3.6 V | 6 | |
| ADC positive reference voltage VREF+ | VDDA ≥ 2 V; maximum VDDA | min 2 V | 6 |
| Operative ambient temperature Tamb | Actual operative range can be limited by thermal shutdown. | min -40 · max 125 °C | 6 |
| Junction-to-ambient thermal resistance RthJA | Natural convection, according to JESD51-2a; 2s2p JEDEC JESD51-7 board, 114.3 x 76.2 x 1.6 mm, ambient 25°C | typ 48.3 °C/W | 7 |
| Junction-to-top characterization parameter ΨJT | According to JESD51-2a; 2s2p JEDEC JESD51-7 board, 114.3 x 76.2 x 1.6 mm, ambient 25°C | typ 1.6 °C/W | 7 |
| Junction-to-board characterization parameter ΨJB | According to JESD51-2a; 2s2p JEDEC JESD51-7 board, 114.3 x 76.2 x 1.6 mm, ambient 25°C | typ 32 °C/W | 7 |
| Human Body Model HBM | Conforming to ANSI/ESDA/JEDEC JS-001-2014 | max 2 kV | 7 |
| Charge Device Model CDM | All pins; Conforming to ANSI/ESDA/JEDEC JS-002-2014 | max 500 V | 7 |
| Charge Device Model CDM | Corner pins only; Conforming to ANSI/ESDA/JEDEC JS-002-2014 | max 750 V | 7 |
| Control logic turn-on threshold VREG3V3(On) | VREG3V3 rising | max 2.5 V | 8 |
| Control logic turn-off threshold VREG3V3(Off) | VREG3V3 falling | min 1.9 V | 8 |
| Control logic turn-off threshold during standby VREG3V3Stby(Off) | VREG3V3 falling | typ 2.4 V | 8 |
| Control logic quiescent consumption IREG3V3,qu | MCU consumption excluded; Tamb = 25°C | typ 1.9 · max 3 mA | 8 |
| VCC UVLO turn-on threshold VCC(On) | VCC rising | max 5.5 V | 8 |
| VCC UVLO hysteresis VCC(Hyst) | VCC falling | min 70 mV | 8 |
| VCC quiescent consumption ICC,qu | typ 850 · max 1700 uA | 8 | |
| VBOOT - VOUT UVLO turn-on threshold VBO(On) | VBOOT rising | max 5 V | 8 |
| VBOOT - VOUT UVLO hysteresis VBO(Hyst) | VBOOT falling | min 100 mV | 8 |
| VBOOT - VOUT quiescent current IBO,qu | typ 170 · max 250 uA | 8 | |
| VM quiescent consumption IM,qu | VCC = 15 V ext; All gate driver outputs low. | typ 1500 · max 3000 uA | 8 |
| Regulator turn-on threshold VON,Buck | VM rising | min 3 · max 4.5 V | 8 |
| Regulator turn-off hysteresis VHyst,Buck | VM falling | min 50 · typ 150 · max 250 mV | 8 |
| Regulated output voltage VCC,mean | Set to 8 V, mean value | min 7.2 · typ 8 · max 8.8 V | 8 |
| Regulated output voltage VCC,mean | Set to 10 V, mean value | min 9 · typ 10 · max 11 V | 8 |
| Regulated output voltage VCC,mean | Set to 12 V, mean value | min 10.8 · typ 12 · max 13.2 V | 8 |
| Regulated output voltage VCC,mean | Set to 15 V, mean value | min 13.5 · typ 15 · max 16.5 V | 8 |
| Peak-to-peak output ripple VCC,PkPk | Percentage referred to target VCC | typ 1.875 % | 8 |
| Peak current threshold Ipeak,Buck | typ 750 mA | 8 | |
| Switching frequency fSW,Buck | typ 500 kHz | 8 | |
| Minimum buck ON-time tON,Buck, min | max 220 ns | 8 | |
| Minimum buck OFF-time tOFF,Buck min | typ 220 ns | 8 | |
| PMOS switch on-resistance RDS(ON),SW | typ 3 Ω | 8 | |
| Soft-start time tSS,Buck | typ 3.3 ms | 8 | |
| Soft-start switching frequency fSW,SS | typ 60 kHz | 8 | |
| Disable time tdisable,Buck | typ 4 ms | 8 | |
| Buck converter overcurrent threshold IOC,Buck | typ 1.2 A | 9 | |
| Shutdown temperature TSD | VCC buck regulator | min 140 · max 160 °C | 9 |
| Thermal shutdown hysteresis TSD(Hyst) | VCC buck regulator | typ 30 °C | 9 |
| 3.3 V linear regulator output and logic supply voltage VREG3V3 | VREGIN = 5 V; IREG3V3 = 150 mA | min 3.1 · typ 3.3 · max 3.5 V | 9 |
| 3.3 V linear regulator current limit IREG3V3lim | REG3V3 shorted to ground | min 151 mA | 9 |
| Shutdown temperature TSD | 3.3 V Linear regulator | min 140 · max 160 °C | 9 |
| Thermal shutdown hysteresis TSD(Hyst) | 3.3 V Linear regulator | typ 30 °C | 9 |
| Sink/source current capabilities Igate | VCC = 5.5 V to 15 V; VBOx = 5.5 V to 15 V; Tamb = 25°C | min 700 · typ 1000 · max 1300 mA | 9 |
| Sink/source current capabilities Igate | VCC = 5.5 V to 15 V; VBOx = 5.5 V to 15 V; Full temperature range | min 500 · max 1500 mA | 9 |
| PMOS on-resistance RPMOS | VCC = 12 V, VBOx = 12 V; Isource = 100 mA; Tamb = 25°C | typ 3.7 Ω | 9 |
| PMOS on-resistance RPMOS | VCC = 12 V, VBOx = 12 V; Isource = 100 mA; Full temperature range | max 5.8 Ω | 9 |
| NMOS on-resistance RNMOS | VCC = 12 V, VBOx = 12 V; Isink = 100 mA; Tamb = 25°C | typ 1.6 Ω | 9 |
| NMOS on-resistance RNMOS | VCC = 12 V, VBOx = 12 V; Isink = 100 mA; Full temperature range | max 2.6 Ω | 9 |
| Deadtime tDT | Minimum deadtime enabled | typ 150 ns | 9 |
| OUTx bias current IOUTx,bias | VOUTx = VM = 60 V, VBOx = 15 V | typ 180 · max 260 uA | 9 |
| OUTx bias current IOUTx,bias | VOUTx = 0 V, VBOx = 15 V | typ 180 · max 260 uA | 9 |
| Input to output propagation delay ton, toff | VCC = 5.5 V to 15 V; VBOx = 5.5 V to 15 V | typ 30 · max 60 ns | 9 |
| Input to output propagation delay ton, toff | VCC = 5.5 V to 15 V; VBOx = 5.5 V to 15 V; Full temperature range | max 120 ns | 9 |
| Delay matching, HS and LS turn-on/off MT | (1) | typ 0 · max 50 ns | 9 |
| Delay matching between channels MTCH | (2) | typ 0 · max 50 ns | 10 |
| Bootstrap diode on-resistance RDS_diode | typ 100 · max 200 Ω | 10 | |
| Input lines pull-down resistor RPDin | typ 500 kΩ | 10 | |
| Fault reset time tFAULT,reset | max 160 us | 10 | |
| I2C lines pull-up resistors RPU,I2C | typ 4 kΩ | 10 | |
| I2C speed I2C speed | min 0.1 · max 1 Mbps | 10 | |
| Overall standby consumption from VM ISTBY | VM = 75 V; Standby regulator enabled, MCU consumption excluded | typ 15 · max 30 uA | 10 |
| Standby time tSTBY | typ 100 us | 10 | |
| Standby regulator output voltage VREGStby | VM = 5 V; IREG3V3 = 1 mA | min 3 · typ 3.3 · max 3.6 V | 10 |
| Standby regulator current limit IREGStby,lim | VM = 5.5 V, Tamb = 25°C | min 5 mA | 10 |
| 3.3V LDO wake-up time tWAKE,LDO | typ 10 us | 10 | |
| VDS monitoring protection threshold VDSth | VSCREF = 0.2 V, Tamb = 25°C | min 0.1 · typ 0.2 · max 0.3 V | 10 |
| VDS monitoring protection threshold VDSth | VSCREF = 1 V, Tamb = 25°C | min 0.8 · typ 1 · max 1.2 V | 10 |
| VDS monitoring protection threshold VDSth | VSCREF = 2.5 V, Tamb = 25°C | min 2.2 · typ 2.5 · max 2.8 V | 10 |
| VDS monitoring protection enable voltage VSCREF,en | max 2.55 V | 10 | |
| VDS monitoring protection disable voltage VSCREF,dis | min 2.9 V | 10 | |
| VDS monitoring protection reference pull-down resistor RSCREF | typ 400 kΩ | 10 | |
| VDS monitoring protection deglitch filter time tDFSC | VDS_P_DEG = 00 | typ 6 us | 10 |
| VDS monitoring protection deglitch filter time tDFSC | VDS_P_DEG = 01 | typ 4 us | 10 |
| VDS monitoring protection deglitch filter time tDFSC | VDS_P_DEG = 10 | typ 3 us | 10 |
| VDS monitoring protection deglitch filter time tDFSC | VDS_P_DEG = 11 | typ 2 us | 10 |
Pins, by the datasheet
38- 1 REG3V3/VDD
- 3.3V LDO regulator output and control logic supply voltage. · p. 11
- 2 VBAT
- MCU backup supply. · p. 11
- 3 PC13
- TIM8_CH4N, TIM1_BKIN, EVENTOUT, WKUP2, RTC_TAMP1, RTC_TS, RTC_OUT1. · p. 11
- 4 PC14
- EVENTOUT, OSC32_IN. · p. 11
- 5 PC15
- EVENTOUT, OSC32_OUT. · p. 11
- 6 PF0
- I2C2_SDA, SPI2_NSS/I2S2_WS, EVENTOUT, ADC1_IN10, OSC_IN. · p. 11
- 7 PF1
- SPI2_SCK/I2S2_CK, EVENTOUT, ADC2_IN10, COMP3_INM, OSC_OUT. · p. 11
- 8 PG10
- MCO, EVENTOUT, NRST. · p. 11
- 9 PC0
- LPTIM1_IN1, LPUART1_RX, EVENTOUT, ADC12_IN6, COMP3_INM. · p. 11
- 10 PC1
- LPTIM1_OUT, LPUART1_TX, SAI1_SD_A, EVENTOUT, ADC12_IN7, COMP3_INP. · p. 11
- 11 PC2
- LPTIM1_IN2, COMP3_OUT, EVENTOUT, ADC12_IN8. · p. 11
- 33 NC
- NC in the pin connection diagram. · p. 11
- 34 NC
- NC in the pin connection diagram. · p. 11
- 40 GHS2
- Phase 2 high-side driver output. · p. 13
- 41 BOOT1
- Phase 1 bootstrap supply voltage. · p. 13
- 42 OUT1
- Phase 1 high-side (floating) common voltage. · p. 13
- 43 GHS1
- Phase 1 high-side driver output. · p. 13
- 44 PA8
- MCO, I2C2_SDA, I2S2_MCK, USART1_CK, TIM4_ETR, SAI1_CK2, SAI1_SCK_A, EVENTOUT. · p. 13
- 45 PA9
- I2C2_SCL, I2S3_MCK, USART1_TX, TIM15_BKIN, TIM2_CH3, SAI1_FS_A, EVENTOUT, UCPD1_DBCC1. · p. 13
- 46 PA10
- TIM17_BKIN, USB_CRS_SYNC, I2C2_SMBA, SPI2_MISO, USART1_RX, TIM2_CH4, TIM8_BKIN, SAI1_D1, SAI1_SD_A, EVENTOUT, UCPD1_DBCC2. · p. 13
- 47 PA11
- TIM1_BKIN2, SPI2_MOSI/I2S2_SD, USART1_CTS, COMP1_OUT, FDCAN1_RX, TIM4_CH1, EVENTOUT, USB_DM. · p. 13
- 48 PA12
- TIM16_CH1, I2SCKIN, USART1_RTS_DE, COMP2_OUT, FDCAN1_TX, TIM4_CH2, EVENTOUT, USB_DP. · p. 13
- 49 PA13
- SWDIO-JTMS, TIM16_CH1N, I2C1_SCL, IR_OUT, USART3_CTS, TIM4_CH3, SAI1_SD_B, EVENTOUT. · p. 13
- 50 PA14
- SWCLK-JTCK, LPTIM1_OUT, I2C1_SDA, TIM8_CH2, TIM1_BKIN, USART2_TX, SAI1_FS_B, EVENTOUT. · p. 13
- 51 PA15
- JTDI, TIM2_CH1, TIM8_CH1, TIM1_BKIN, I2C1_SCL, SPI1_NSS, SPI3_NSS/I2S3_WS, USART2_RX, UART4_RTS_DE, TIM2_ETR, EVENTOUT. · p. 13
- 52 SCREF
- Sets the short-circuit protection threshold; a voltage above VSCREF,dis disables the protection. · p. 13
- 53 PD2
- TIM3_ETR, TIM8_BKIN, EVENTOUT. · p. 13
- 54 PB3
- JTDO-TRACESWO, TIM2_CH2, TIM4_ETR, USB_CRS_SYNC, TIM8_CH1N, SPI1_SCK, SPI3_SCK/I2S3_CK, USART2_TX, TIM3_ETR, SAI1_SCK_B, EVENTOUT. · p. 13
- 55 PB4
- JTRST, TIM16_CH1, TIM3_CH1, TIM8_CH2N, SPI1_MISO, SPI3_MISO, USART2_RX, TIM17_BKIN, SAI1_MCLK_B, EVENTOUT, UCPD1_CC2. · p. 13
- 56 PB5
- TIM16_BKIN, TIM3_CH2, TIM8_CH3N, I2C1_SMBA, SPI1_MOSI, SPI3_MOSI/I2S3_SD, USART2_CK, TIM17_CH1, LPTIM1_IN1, SAI1_SD_B, EVENTOUT. · p. 13
- 57 PB6
- TIM16_CH1N, TIM4_CH1, TIM8_CH1, TIM8_ETR, USART1_TX, COMP4_OUT, TIM8_BKIN2, LPTIM1_ETR, SAI1_FS_B, EVENTOUT, UCPD1_CC1. · p. 13
- 58 PB7
- TIM17_CH1N, TIM4_CH2, I2C1_SDA, TIM8_BKIN, USART1_RX, COMP3_OUT, TIM3_CH4, LPTIM1_IN2, UART4_CTS, EVENTOUT, PVD_IN. · p. 13
- 59 PB8
- MCU PB8-BOOT0; TIM1_BKIN, TIM16_CH1, TIM4_CH3, SAI1_CK1, I2C1_SCL, USART3_RX, COMP1_OUT, FDCAN1_RX, TIM8_CH2, SAI1_MCLK_A, EVENTOUT. · p. 13
- 60 PB9
- TIM17_CH1, TIM4_CH4, SAI1_D2, I2C1_SDA, IR_OUT, USART3_TX, COMP2_OUT, FDCAN1_TX, TIM8_CH3, SAI1_FS_A, EVENTOUT. · p. 13
- 61 VM
- Power supply voltage (Motor supply voltage). · p. 13
- 62 SW
- Buck regulator switching output. · p. 13
- 63 VCC
- Gate driver supply voltage. · p. 13
- 64 REGIN
- 3.3 V LDO regulator input. · p. 13
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Questions
Is there a KiCad symbol and footprint for the STSPIN32G4?
Yes. The symbol is EasyEDA_Cloud:STSPIN32G4 and the footprint EasyEDA_Cloud:VFQFPN-64_L9.0-W9.0-P0.50-TL-EP4.0, both drawn on this page. PCBKit places them on a board for you when you design with it.
What package is the STSPIN32G4?
VFQFPN-64(9x9), with 65 pins. Its footprint is drawn on this page.
Where is the STSPIN32G4 datasheet?
STMicroelectronics publishes it: the Datasheet link on this page opens it.
Where can I order the STSPIN32G4?
JLCPCB lists it as part C7434864, with 210 in stock; the sellers' links on this page open their listings.
Which open-source boards use the STSPIN32G4?
20 boards in 16 repositories on GitHub; the most starred are listed on this page, with their KiCad files.