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STM32MP157CAA3 on a board, in 3D

STM32MP157CAA3

STMicroelectronics

-40℃~+125℃ 1.71V~3.6V 12bit 16bit 176 209MHz、650MHz 32 Bit 708KB ARM Cortex-ASeries Built-in+External Power-on reset (POR)、Power-down reset (PDR)、Undervoltage detection (BOR/LVD/LVR/LVI)、Software reset、External pin reset (NRST)、Integrated LDO、Calendar function、Independent watchdog (IWDG)、Window watchdog (WWDG)、Integrated PLL clock generator LFBGA-448 Microcontrollers (MCU/MPU/SOC) ROHS

Extended
DatasheetJLCPCBLCSCst/STM32MP157CAA3
Category
Microcontrollers (MCU, MPU, SOC)
Package
LFBGA-448
Pins
448

Overview

The STM32MP157CAA3 is a microcontroller made by STMicroelectronics in a LFBGA-448 package with 448 pins. -40℃~+125℃ 1.71V~3.6V 12bit 16bit 176 209MHz、650MHz 32 Bit 708KB ARM Cortex-ASeries Built-in+External Power-on reset (POR)、Power-down reset (PDR)、Undervoltage detection (BOR/LVD/LVR/LVI)、Software reset、External pin reset (NRST)、Integrated LDO、Calendar function、Independent watchdog (IWDG)、Window watchdog (WWDG)、Integrated PLL clock generator LFBGA-448 Microcontrollers (MCU/MPU/SOC) ROHS.

PCBKit's library has its KiCad symbol (MCU_ST_STM32MP1:STM32MP157CAAx, from KiCad's library) and its footprint (Package_BGA:ST_LFBGA-448_18x18mm_Layout22x22_P0.8mm, from KiCad's library), ready for a KiCad board. JLCPCB lists it (part C1555550).

Symbol

VSSA1PH5A2PH4A3PE13A4PK6A5PK4A6PJ13A7PD10A8PD5A9PE3A10PA9A11PB3A12PB14A13VDD_DSIA14DSIHOST_D0NA15DSIHOST_CKNA16DSIHOST_D1NA17VDD1V2_DSI_PHYA18DDR_DQ20A20DDR_DQ23A21PG13AA1PG14AA2PA0AA3PB1AA5PC5AA6PB12AA7PB5AA8PG10AA9PF7AA10PF6AA11BYPASS_REG1V8AA12USB_DM2AA14USB_DP1AA15USB_RREFAA17DDR_ATOAA19DDR_DQ29AA20DDR_DQ28AA21DDR_DQM3AA22PA2AB2PC1AB3PG4AB4PB0AB5PC4AB6PH2AB7PB8AB8PD11AB9PF8AB10PF9AB11VDDA1V8_REGAB12VDD3V3_USBHSAB13USB_DP2AB14USB_DM1AB15VDD3V3_USBFSAB16VDDA1V1_REGAB17DDR_VREFAB19DDR_DQ27AB20DDR_DQ26AB21PH10B1PH11B3PE14B4PK7B5PK3B6PJ14B7PJ12B8PF1B9PD1B10PD3B11PB15B12PA8B13VDDA1V8_DSIB14DSIHOST_D0PB15DSIHOST_CKPB16DSIHOST_D1PB17VDD1V2_DSI_REGB18DDR_DQ19B20DDR_DQ16B21DDR_DQS2NB22PH15C1PH14C2PE15C4PE0C5PK5C6PJ15C7PD4C9PD0C10PE5C12PB4C13VSS_DSIC14DDR_DQS2PC21DDR_DQM2C22PI0D1PI14D2PH13D3PE11D5PH8D6PE1D7PK0D8PF5D9PG15D10PG6D11PD2D12PC7D13PC9D14PC11D15JTDID16JTCKD17VDD_PLL2D18VSS_PLL2D19DDR_DQ22D20DDR_DQ17D21DDR_DQ18D22PI2E1PI1E2PI3E3PE12E4PH9E6PK1E7PK2E8PE6E9PF0E10PA15E11PC12E12PC6E13PC8E14NJTRSTE15JTDOE16JTMSE17VDDQ_DDRE18DDR_DQ3E20DDR_DQ0E21DDR_DQ21E22PI7F1PI5F2PI15F3PZ3F4PH12F5PF4F9PD7F10PB7F11PB9F12PF2F13PC10F14PE4F15VDDQ_DDRF17DDR_A7F18DDR_RESETNF19DDR_DQ1F21PZ4G1PZ0G2PZ6G3PI6G5VDDQ_DDRG16DDR_A13G18DDR_DQ7G19DDR_DQM0G20DDR_DQS0NG21DDR_DQS0PG22PI13H1PI12H2PZ7H3PZ5H4PZ1H5PJ8H6VDDCOREH9VDDCOREH11VDDCOREH13VDDCOREH15VDDQ_DDRH17DDR_A9H18DDR_A5H19DDR_DQ5H20DDR_DQ2H21DDR_DQ6H22PJ3J1PJ0J2PJ10J3PG12J4PI9J5PI4J6VDDCOREJ8VDDCOREJ10VDDCOREJ12VDDCOREJ14VDDQ_DDRJ16DDR_A2J18DDR_A3J19DDR_DQ4J21PJ5K1PJ4K2PJ2K4PZ2K5PJ11K6VDDCOREK9VDDCOREK11VDDCOREK13VDDCOREK15VDDQ_DDRK17DDR_BA2K18DDR_A0K19DDR_BA0K20DDR_DTO1K21DDR_ZQK22PD15L1PJ9L2PD6L3PJ7L4PJ6L5PJ1L6VDDCOREL8VDDCOREL10VDDCOREL12VDDCOREL14VDDQ_DDRL16DDR_CSNL18DDR_ODTL21DDR_DTO0L22PD8M1PD9M2PD14M3VBATM4VSS_PLLM5VDD_PLLM6VDDM9VDDCOREM11VDDCOREM13VDDCOREM15VDDQ_DDRM17DDR_A1M18DDR_A15M19DDR_RASNM20DDR_WENM21DDR_CASNM22PI8N1PC13N2BOOT0N3BOOT1N4VDD_ANAN5VREF-N6VDDN8VDDN10VDDCOREN12VDDCOREN14VDDQ_DDRN16DDR_A10N18DDR_A12N19DDR_CLKPN20DDR_CLKNN21DDR_DQ8N22PC14P1PC15P2BOOT2P4VSS_ANAP5VREF+P6VDDP9VDDP11VDDCOREP13VDDCOREP15VDDQ_DDRP17DDR_A14P18DDR_A11P19DDR_DQ10P21NRST_CORER1NRSTR2PA14R3ANA0R4VDDAR5VSSAR6VDDR10VDDR12VDDCORER14VDDQ_DDRR16DDR_BA1R18DDR_CKER19DDR_DQ13R20DDR_DQ9R21DDR_DQS1NR22PH0T1PH1T2PI11T3PA3T4ANA1T5VDDT13VDDCORET15VDDQ_DDRT17DDR_A4T18DDR_DQ11T20DDR_DQM1T21DDR_DQS1PT22PWR_LPU1PDR_ON_COREU2PC3U3PG3U4PA5U5PG5U8VDDU9PC0U10PG11U11VDDU12VDDU14VDDQ_DDRU16DDR_A8U18DDR_A6U19DDR_DQ14U21PWR_ONV1PDR_ONV2PF3V3PA1V4PA4V6PF14V7PF12V8PB10V9PB13V10PH6V11PF10V12PB2V13PD13V14OTG_VBUSV15VDDQ_DDRV17DDR_DQ12V20DDR_DQ15V21DDR_DQ24V22PI10W1PH7W2PA13W3PG2W4PG0W5PF15W6PF13W7PF11W8PA6W9PE7W10PE9W11PD12W12PB6W13PE10W14PG9W15PA12W16VDDQ_DDRW18DDR_DQ25W20DDR_DQ31W21DDR_DQ30W22PC2Y1PE2Y2PG1Y4PB11Y5PH3Y6PG8Y8PA7Y9PG7Y11PE8Y12VSS_USBHSY13PA11Y16PA10Y17VDDQ_DDRY19DDR_DQS3PY21DDR_DQS3NY22
MCU_ST_STM32MP1:STM32MP157CAAxFrom KiCad's library

Footprint

Package_BGA:ST_LFBGA-448_18x18mm_Layout22x22_P0.8mmFrom KiCad's library

Parameters

11
ADC (Bit)
16bit
CPU Core
ARM Cortex-ASeries
CPU Maximum Speed
209MHz, 650MHz
Core Size
32 Bit
DAC (Bit)
12bit
Features
Power-on reset (POR), Power-down reset (PDR), Undervoltage detection (BOR/LVD/LVR/LVI), Software reset, External pin reset (NRST), Integrated LDO, Calendar function, Independent watchdog (IWDG), Window watchdog (WWDG), Integrated PLL clock generator
Number of I/O
176
Operating Temperature
-40℃~+125℃
Oscillator Type
Built-in+External
RAM Size
708KB
Voltage - Supply
1.71V~3.6V

Order codes

1

Pinout

448
The pins of the STM32MP157CAA3
PinNameType
A1VSSPower in
A2PH5Input/output
A3PH4Input/output
A4PE13Input/output
A5PK6Input/output
A6PK4Input/output
A7PJ13Input/output
A8PD10Input/output
A9PD5Input/output
A10PE3Input/output
A11PA9Input/output
A12PB3Input/output
A13PB14Input/output
A14VDD_DSIPower in
A15DSIHOST_D0NInput/output
A16DSIHOST_CKNInput/output
A17DSIHOST_D1NInput/output
A18VDD1V2_DSI_PHYPower in
A19VSSPassive
A20DDR_DQ20Input/output
A21DDR_DQ23Input/output
A22VSSPassive
AA1PG13Input/output
AA2PG14Input/output
AA3PA0Input/output
AA4VSSPassive
AA5PB1Input/output
AA6PC5Input/output
AA7PB12Input/output
AA8PB5Input/output
AA9PG10Input/output
AA10PF7Input/output
AA11PF6Input/output
AA12BYPASS_REG1V8Input/output
AA13VSS_USBHSPassive
AA14USB_DM2Input/output
AA15USB_DP1Input/output
AA16VSS_USBHSPassive
AA17USB_RREFInput/output
AA18VSSPassive
AA19DDR_ATOInput/output
AA20DDR_DQ29Input/output
AA21DDR_DQ28Input/output
AA22DDR_DQM3Input/output
AB1VSSPassive
AB2PA2Input/output
AB3PC1Input/output
AB4PG4Input/output
AB5PB0Input/output
AB6PC4Input/output
AB7PH2Input/output
AB8PB8Input/output
AB9PD11Input/output
AB10PF8Input/output
AB11PF9Input/output
AB12VDDA1V8_REGPower in
AB13VDD3V3_USBHSPower in
AB14USB_DP2Input/output
AB15USB_DM1Input/output
AB16VDD3V3_USBFSPower in
AB17VDDA1V1_REGPower in
AB18VSSPassive
AB19DDR_VREFInput/output
AB20DDR_DQ27Input/output
AB21DDR_DQ26Input/output
AB22VSSPassive
B1PH10Input/output
B2VSSPassive
B3PH11Input/output
B4PE14Input/output
B5PK7Input/output
B6PK3Input/output
B7PJ14Input/output
B8PJ12Input/output
B9PF1Input/output
B10PD1Input/output
B11PD3Input/output
B12PB15Input/output
B13PA8Input/output
B14VDDA1V8_DSIPower in
B15DSIHOST_D0PInput/output
B16DSIHOST_CKPInput/output
B17DSIHOST_D1PInput/output
B18VDD1V2_DSI_REGPower in
B19VSSPassive
B20DDR_DQ19Input/output
B21DDR_DQ16Input/output
B22DDR_DQS2NInput/output
C1PH15Input/output
C2PH14Input/output
C3VSSPassive
C4PE15Input/output
C5PE0Input/output
C6PK5Input/output
C7PJ15Input/output
C8VSSPassive
C9PD4Input/output
C10PD0Input/output
C11VSSPassive
C12PE5Input/output
C13PB4Input/output
C14VSS_DSIPower in
C15VSS_DSIPassive
C16VSS_DSIPassive
C17VSS_DSIPassive
C18VSS_DSIPassive
C19VSSPassive
C20VSSPassive
C21DDR_DQS2PInput/output
C22DDR_DQM2Input/output
D1PI0Input/output
D2PI14Input/output
D3PH13Input/output
D4VSSPassive
D5PE11Input/output
D6PH8Input/output
D7PE1Input/output
D8PK0Input/output
D9PF5Input/output
D10PG15Input/output
D11PG6Input/output
D12PD2Input/output
D13PC7Input/output
D14PC9Input/output
D15PC11Input/output
D16JTDIInput/output
D17JTCKInput/output
D18VDD_PLL2Power in
D19VSS_PLL2Power in
D20DDR_DQ22Input/output
D21DDR_DQ17Input/output
D22DDR_DQ18Input/output
E1PI2Input/output
E2PI1Input/output
E3PI3Input/output
E4PE12Input/output
E5VSSPassive
E6PH9Input/output
E7PK1Input/output
E8PK2Input/output
E9PE6Input/output
E10PF0Input/output
E11PA15Input/output
E12PC12Input/output
E13PC6Input/output
E14PC8Input/output
E15NJTRSTInput/output
E16JTDOInput/output
E17JTMSInput/output
E18VDDQ_DDRPower in
E19VSSPassive
E20DDR_DQ3Input/output
E21DDR_DQ0Input/output
E22DDR_DQ21Input/output
F1PI7Input/output
F2PI5Input/output
F3PI15Input/output
F4PZ3Input/output
F5PH12Input/output
F6VSSPassive
F7VSSPassive
F8VSSPassive
F9PF4Input/output
F10PD7Input/output
F11PB7Input/output
F12PB9Input/output
F13PF2Input/output
F14PC10Input/output
F15PE4Input/output
F16VSSPassive
F17VDDQ_DDRPower in
F18DDR_A7Input/output
F19DDR_RESETNInput/output
F20VSSPassive
F21DDR_DQ1Input/output
G1PZ4Input/output
G2PZ0Input/output
G3PZ6Input/output
G4VSSPassive
G5PI6Input/output
G6VSSPassive
G8VSSPassive
G10VSSPassive
G12VSSPassive
G14VSSPassive
G16VDDQ_DDRPower in
G17VSSPassive
G18DDR_A13Input/output
G19DDR_DQ7Input/output
G20DDR_DQM0Input/output
G21DDR_DQS0NInput/output
G22DDR_DQS0PInput/output
H1PI13Input/output
H2PI12Input/output
H3PZ7Input/output
H4PZ5Input/output
H5PZ1Input/output
H6PJ8Input/output
H7VSSPassive
H9VDDCOREPower in
H11VDDCOREPower in
H13VDDCOREPower in
H15VDDCOREPower in
H17VDDQ_DDRPower in
H18DDR_A9Input/output
H19DDR_A5Input/output
H20DDR_DQ5Input/output
H21DDR_DQ2Input/output
H22DDR_DQ6Input/output
J1PJ3Input/output
J2PJ0Input/output
J3PJ10Input/output
J4PG12Input/output
J5PI9Input/output
J6PI4Input/output
J8VDDCOREPower in
J9VSSPassive
J10VDDCOREPower in
J11VSSPassive
J12VDDCOREPower in
J13VSSPassive
J14VDDCOREPower in
J16VDDQ_DDRPower in
J17VSSPassive
J18DDR_A2Input/output
J19DDR_A3Input/output
J20VSSPassive
J21DDR_DQ4Input/output
K1PJ5Input/output
K2PJ4Input/output
K3VSSPassive
K4PJ2Input/output
K5PZ2Input/output
K6PJ11Input/output
K7VSSPassive
K9VDDCOREPower in
K10VSSPassive
K11VDDCOREPower in
K12VSSPassive
K13VDDCOREPower in
K14VSSPassive
K15VDDCOREPower in
K17VDDQ_DDRPower in
K18DDR_BA2Input/output
K19DDR_A0Input/output
K20DDR_BA0Input/output
K21DDR_DTO1Input/output
K22DDR_ZQInput/output
L1PD15Input/output
L2PJ9Input/output
L3PD6Input/output
L4PJ7Input/output
L5PJ6Input/output
L6PJ1Input/output
L8VDDCOREPower in
L9VSSPassive
L10VDDCOREPower in
L11VSSPassive
L12VDDCOREPower in
L13VSSPassive
L14VDDCOREPower in
L16VDDQ_DDRPower in
L17VSSPassive
L18DDR_CSNInput/output
L19VSSPassive
L20VSSPassive
L21DDR_ODTInput/output
L22DDR_DTO0Input/output
M1PD8Input/output
M2PD9Input/output
M3PD14Input/output
M4VBATPower in
M5VSS_PLLPower in
M6VDD_PLLPower in
M7VSSPassive
M9VDDPower in
M10VSSPassive
M11VDDCOREPower in
M12VSSPassive
M13VDDCOREPower in
M14VSSPassive
M15VDDCOREPower in
M17VDDQ_DDRPower in
M18DDR_A1Input/output
M19DDR_A15Input/output
M20DDR_RASNInput/output
M21DDR_WENInput/output
M22DDR_CASNInput/output
N1PI8Input/output
N2PC13Input/output
N3BOOT0Input
N4BOOT1Input
N5VDD_ANAPower in
N6VREF-Input
N8VDDPower in
N9VSSPassive
N10VDDPower in
N11VSSPassive
N12VDDCOREPower in
N13VSSPassive
N14VDDCOREPower in
N16VDDQ_DDRPower in
N17VSSPassive
N18DDR_A10Input/output
N19DDR_A12Input/output
N20DDR_CLKPInput/output
N21DDR_CLKNInput/output
N22DDR_DQ8Input/output
P1PC14Input/output
P2PC15Input/output
P3VSSPassive
P4BOOT2Input
P5VSS_ANAPower in
P6VREF+Input
P7VSSPassive
P9VDDPower in
P10VSSPassive
P11VDDPower in
P12VSSPassive
P13VDDCOREPower in
P14VSSPassive
P15VDDCOREPower in
P17VDDQ_DDRPower in
P18DDR_A14Input/output
P19DDR_A11Input/output
P20VSSPassive
P21DDR_DQ10Input/output
R1NRST_COREInput
R2NRSTInput
R3PA14Input/output
R4ANA0Input/output
R5VDDAPower in
R6VSSAPower in
R8VSSPassive
R10VDDPower in
R12VDDPower in
R14VDDCOREPower in
R16VDDQ_DDRPower in
R17VSSPassive
R18DDR_BA1Input/output
R19DDR_CKEInput/output
R20DDR_DQ13Input/output
R21DDR_DQ9Input/output
R22DDR_DQS1NInput/output
T1PH0Input/output
T2PH1Input/output
T3PI11Input/output
T4PA3Input/output
T5ANA1Input/output
T6VSSAPassive
T7VSSPassive
T9VSSPassive
T11VSSPassive
T13VDDPower in
T15VDDCOREPower in
T17VDDQ_DDRPower in
T18DDR_A4Input/output
T19VSSPassive
T20DDR_DQ11Input/output
T21DDR_DQM1Input/output
T22DDR_DQS1PInput/output
U1PWR_LPOutput
U2PDR_ON_COREInput/output
U3PC3Input/output
U4PG3Input/output
U5PA5Input/output
U6VSSAPassive
U7VSSPassive
U8PG5Input/output
U9VDDPower in
U10PC0Input/output
U11PG11Input/output
U12VDDPower in
U13VSSPassive
U14VDDPower in
U15VSSPassive
U16VDDQ_DDRPower in
U17VSSPassive
U18DDR_A8Input/output
U19DDR_A6Input/output
U20VSSPassive
U21DDR_DQ14Input/output
V1PWR_ONOutput
V2PDR_ONInput/output
V3PF3Input/output
V4PA1Input/output
V5VSSPassive
V6PA4Input/output
V7PF14Input/output
V8PF12Input/output
V9PB10Input/output
V10PB13Input/output
V11PH6Input/output
V12PF10Input/output
V13PB2Input/output
V14PD13Input/output
V15OTG_VBUSInput/output
V16VSSPassive
V17VDDQ_DDRPower in
V18VSSPassive
V19VSSPassive
V20DDR_DQ12Input/output
V21DDR_DQ15Input/output
V22DDR_DQ24Input/output
W1PI10Input/output
W2PH7Input/output
W3PA13Input/output
W4PG2Input/output
W5PG0Input/output
W6PF15Input/output
W7PF13Input/output
W8PF11Input/output
W9PA6Input/output
W10PE7Input/output
W11PE9Input/output
W12PD12Input/output
W13PB6Input/output
W14PE10Input/output
W15PG9Input/output
W16PA12Input/output
W17VSSPassive
W18VDDQ_DDRPower in
W19VSSPassive
W20DDR_DQ25Input/output
W21DDR_DQ31Input/output
W22DDR_DQ30Input/output
Y1PC2Input/output
Y2PE2Input/output
Y3VSSPassive
Y4PG1Input/output
Y5PB11Input/output
Y6PH3Input/output
Y7VSSPassive
Y8PG8Input/output
Y9PA7Input/output
Y10VSSPassive
Y11PG7Input/output
Y12PE8Input/output
Y13VSS_USBHSPower in
Y14VSS_USBHSPassive
Y15VSS_USBHSPassive
Y16PA11Input/output
Y17PA10Input/output
Y18VSSPassive
Y19VDDQ_DDRPower in
Y20VSSPassive
Y21DDR_DQS3PInput/output
Y22DDR_DQS3NInput/output

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Questions

Is there a KiCad symbol and footprint for the STM32MP157CAA3?

Yes. The symbol is MCU_ST_STM32MP1:STM32MP157CAAx and the footprint Package_BGA:ST_LFBGA-448_18x18mm_Layout22x22_P0.8mm, both drawn on this page. PCBKit places them on a board for you when you design with it.

What package is the STM32MP157CAA3?

LFBGA-448, with 448 pins. Its footprint is drawn on this page.

Where is the STM32MP157CAA3 datasheet?

STMicroelectronics publishes it: the Datasheet link on this page opens it.

Where can I order the STM32MP157CAA3?

JLCPCB lists it as part C1555550, with 0 in stock; the sellers' links on this page open their listings.

What can replace the STM32MP157CAA3?

Parts like it in the library: the STM32MP157AAA3 by STMicroelectronics, the STM32MP151AAA3 by STMicroelectronics, the STM32MP151CAA3 by STMicroelectronics and the STM32MP153CAA3 by STMicroelectronics. Check their datasheets: a part that fits the footprint may still differ in its ratings.

Parts like it

8