SX1280IMLTRT

Q: Is there a KiCad symbol and footprint for the SX1280IMLTRT?

Yes. The symbol is Analog & Interface:SX1280IMLTRT and the footprint ICs And Semiconductors SMD:QFN50P400X400X100-25N-S265, both drawn on this page. PCBKit places them on a board for you when you design with it.

Q: What package is the SX1280IMLTRT?

QFN-24-EP(4x4), with 25 pins. Its footprint is drawn on this page.

Q: Where is the SX1280IMLTRT datasheet?

SEMTECH publishes it: the Datasheet link on this page opens it.

Q: Where can I order the SX1280IMLTRT?

JLCPCB lists it as part C125969, with 3,596 in stock; the sellers' links on this page open their listings.

Q: Which open-source boards use the SX1280IMLTRT?

32 boards in 20 repositories on GitHub; the most starred are listed on this page, with their KiCad files.

SEMTECH

-132dBm -40℃~+85℃ 1.8V~3.7V 12.5dBm 2.4GHz 2.4GHz~2.5GHz 24mA 8.2mA SPI、UART Supports RSSI function transceiver QFN-24-EP(4x4) RF Transceiver ICs ROHS

Extended

Datasheetsemtech/SX1280IMLTRT

Category: RF Transceiver ICs
Package: QFN-24-EP(4x4)
Pins: 25

Overview

The SX1280IMLTRT is a RF Transceiver IC made by SEMTECH in a QFN-24-EP(4x4) package with 25 pins. -132dBm -40℃~+85℃ 1.8V~3.7V 12.5dBm 2.4GHz 2.4GHz~2.5GHz 24mA 8.2mA SPI、UART Supports RSSI function transceiver QFN-24-EP(4x4) RF Transceiver ICs ROHS.

PCBKit's library has its KiCad symbol (Analog & Interface:SX1280IMLTRT, from CERN's library) and its footprint (ICs And Semiconductors SMD:QFN50P400X400X100-25N-S265, from CERN's library), ready for a KiCad board. 3,596 are in stock at JLCPCB (part C125969). 32 open-source boards in 20 repositories on GitHub use it.

Symbol

Analog & Interface:SX1280IMLTRTFrom CERN's library

Footprint

ICs And Semiconductors SMD:QFN50P400X400X100-25N-S265From CERN's library

From the datasheet

Supply, least: 1.8 V · VBAT, recommended operating min · p. 19
Supply, most: 3.7 V · VBAT, recommended operating max · p. 19
Supply, absolute maximum: 3.9 V · VBAT, absolute max · p. 19
Works from: -40 °C · Operating temperature under bias min · p. 19
Works up to: 85 °C · Operating temperature under bias max · p. 19
Junction, hottest: 125 °C · Junction temperature max · p. 154
Takes working: 5.7 mA · sum of VBAT and VBAT_IO, typical FSK receive, low power, BW = 2400 kHz, BR = 2000 kb/s · p. 25
Takes at most: 24 mA · sum of VBAT and VBAT_IO, typical transmit at 12.5 dBm · p. 26
Takes asleep: 215 nA · sum of VBAT and VBAT_IO, typical sleep, data RAM not retained, data buffer retained · p. 20
Data rate, most: 2 Mbit/s · FSK programmable bitrate max · p. 25
Junction to air (QFN 24L 4X4 E-pad): 50.3 K/W · Still air, four-layer JEDEC PCB, nine thermal vias · p. 154
Junction to case (QFN 24L 4X4 E-pad): 30 K/W · Junction to case · p. 154
Junction to board (QFN 24L 4X4 E-pad): 13.3 K/W · Junction to board · p. 154

What it is and has

RF band: 2.4 GHz · p. 1
Receiver sensitivity: Down to -132 dBm · p. 1
Transmitter: +12.5 dBm, high efficiency PA · p. 1
Power regulation: On-chip DC-DC · p. 1
Modulations: LoRa®, FLRC, (G)FSK · p. 1
Ranging: Standard and Advanced Ranging Engine, Time-of-Flight · p. 1
BLE: PHY layer compatibility · p. 1
Package: QFN 24 · p. 2
Environmental compliance: Pb-free, Halogen free, RoHS/WEEE compliant · p. 2
Radio operation: Half-duplex · p. 15
SPI: Slave, up to 18 MHz · p. 60
ESD HBM: Class 2, JESD22-A114, all pins · p. 19
ESD CDM: Class III, JESD22-C101, all pins · p. 19
Package: QFN24 4x4mm (MLP) · p. 154

Specifications

148

Parameter	Conditions	As printed	Page
Supply voltage on VBAT and VBAT_IO VBATmr		min -0.5 · max 3.9 V	19
Temperature Tmr		min -55 · max 115 °C	19
RF Input level Pmr		max 10 dBm	19
Supply voltage VBAT and VBAT_IO VBATop		min 1.8 · max 3.7 V	19
Temperature under bias Top		min -40 · max 85 °C	19
Load capacitance on digital ports Clop		max 10 pF	19
RF Input power ML		max 0 dBm	19
Supply current in Sleep mode IDDSL	data RAM not retained; data buffer retained	typ 0.215 · max 1 uA	20
Supply current in Sleep mode IDDSL	data RAM retained (context saved); data buffer flushed	typ 0.25 · max 1 uA	20
Supply current in Sleep mode IDDSL	data RAM retained; data buffer retained	typ 0.4 · max 1 uA	20
Supply current in Sleep mode IDDSL	data RAM retained; data buffer retained; RC64k is running	typ 1.2 · max 1.8 uA	20
Supply current in STDBY_RC mode IDDSTDBYRC		typ 700 uA	20
Supply current in STDBY_XOSC mode IDDSTDBYXOSC		typ 1 mA	20
Supply current in FS mode IDDFS		typ 2.8 mA	20
Synthesizer frequency range FR		min 2400 · max 2500 MHz	20
Synthesizer frequency step FSTEP	52 MHz reference	typ 198 Hz	20
Phase noise at 2.45 GHz PHN	1 MHz offset	typ -115 dBc/Hz	20
Phase noise at 2.45 GHz PHN	10 MHz offset	typ -135 dBc/Hz	20
Crystal oscillator frequency FXOSC		typ 52 MHz	20
Frequency synthesizer wake-up time with XOSC enabled TS_FS		typ 54 us	20
Frequency synthesizer hop time to within 10 kHz of target frequency TS_HOP	1 MHz	typ 20 us	20
Frequency synthesizer hop time to within 10 kHz of target frequency TS_HOP	10 MHz	typ 30 us	20
Frequency synthesizer hop time to within 10 kHz of target frequency TS_HOP	100 MHz	typ 50 us	20
Crystal oscillator wake-up time from STDBY_RC mode TS_OS		typ 40 us	20
3rd Order input intercept for maximum low power gain setting IIP3	In-band interferer <6 MHz	typ -25 dBm	21
3rd Order input intercept for maximum low power gain setting IIP3	In-band interferer at 6 MHz offset	typ -12 dBm	21
3rd Order input intercept for maximum low power gain setting IIP3	In-band interferer at10 MHz offset	typ 0 dBm	21
3rd Order input intercept for maximum low power gain setting IIP3	In-band interferer at 20 MHz offset	typ 0 dBm	21
Image rejection (CW tone 1% PER) IMR		typ 30 dB	21
Supply current for low power mode IDDRXLP_L	BW = 203 kHz	typ 5.5 mA	22
Supply current for low power mode IDDRXLP_L	BW = 406 kHz	typ 6 mA	22
Supply current for low power mode IDDRXLP_L	BW = 812 kHz	typ 7 mA	22
Supply current for low power mode IDDRXLP_L	BW = 1625 kHz	typ 7.5 mA	22
Supply current for high sensitivity mode IDDRXHS_L	BW = 203 kHz	typ 6.2 mA	22
Supply current for high sensitivity mode IDDRXHS_L	BW = 406 kHz	typ 6.7 mA	22
Supply current for high sensitivity mode IDDRXHS_L	BW = 812 kHz	typ 7.7 mA	22
Supply current for high sensitivity mode IDDRXHS_L	BW = 1625 kHz	typ 8.2 mA	22
LoRa® bitrate programmable range with CR = 4/5 RB_L	SF5, BW = 1625 kHz	typ 202 kb/s	22
LoRa® bitrate programmable range with CR = 4/5 RB_L	SF6, BW = 1625 kHz	typ 122 kb/s	22
LoRa® bitrate programmable range with CR = 4/5 RB_L	SF7, BW = 1625 kHz	typ 71 kb/s	22
LoRa® bitrate programmable range with CR = 4/5 RB_L	SF12, BW = 203 kHz	typ 0.476 kb/s	22
LoRa® bandwidth programmable range BW_L		min 203 · max 1625 kHz	22
LoRa® receiver sensitivity with CR = 4/5 and low power mode enabled RFSLP_L	SF7, BW = 1625 kHz	typ -106 dBm	22
LoRa® receiver sensitivity with CR = 4/5 and low power mode enabled RFSLP_L	SF12, BW = 203 kHz	typ -130 dBm	22
LoRa® receiver sensitivity with CR = 4/5 and high sensitivity mode enabled RFSHS_L	SF7, BW = 1625 kHz	typ -108 dBm	22
LoRa® receiver sensitivity with CR = 4/5 and high sensitivity mode enabled RFSHS_L	SF12, BW = 203 kHz	typ -132 dBm	22
Co-channel rejection LoRa® CCR_L	SF7	typ 7.5 dB	22
Co-channel rejection LoRa® CCR_L	SF12	typ 19.5 dB	22
Blocking immunity SF12 BI_L	+/- 1 MHz	typ 60 dB	22
Blocking immunity SF12 BI_L	+/- 2 MHz	typ 63 dB	22
Blocking immunity SF12 BI_L	+/- 10 MHz	typ 81 dB	22
Adjacent channel rejection at 1.5 BW of CW ACR_L	SF = 12, BW = 203 kHz	typ 37 dB	23
Adjacent channel rejection at 1.5 BW of CW ACR_L	SF = 7, BW = 1.6 MHz	typ 37 dB	23
Maximum tolerated frequency offset between transmitter and receiver, no sensitivity degradation FERR_L	SF12	min -50 · max 50 ppm	23
Maximum tolerated frequency offset between transmitter and receiver, no sensitivity degradation FERR_L	SF5 to SF10	min -80 · max 80 ppm	23
Supply currents (detection mode) IDDRX_FL	BW = 300 kHz, BR = 260 kb/s; BT = 0.5	typ 6.5 mA	24
Supply currents (detection mode) IDDRX_FL	BW = 1200 kHz, BR = 1300 kb/s; BT = 0.5	typ 8.6 mA	24
FLRC Modem programmable bitrate RB_FL	Raw bits; BT = 0.5	min 260 · max 1300 kb/s	24
Programmable channel bandwidth range BW_FL	BT = 0.5	min 300 · max 1200 kHz	24
FLRC Receiver Sensitivity RFS_FL	260 kSymb/s, 130 kb/s; BW = 300 kHz CR=1/2; BT = 0.5	typ -106 dBm	24
FLRC Receiver Sensitivity RFS_FL	1.3 MSymb/s, 650 Mb/s; BW = 1.2 MHz, CR=1/2; BT = 0.5	typ -100.5 dBm	24
Co-channel rejection FLRC CCR_FL	BT = 0.5	typ -10 dB	24
Blocker level for Max low power gain setting BI_FL	+/- 1 MHz; BT = 0.5	typ 41 dB	24
Blocker level for Max low power gain setting BI_FL	+/- 2 MHz; BT = 0.5	typ 44 dB	24
Blocker level for Max low power gain setting BI_FL	+/- 10 MHz; BT = 0.5	typ 62 dB	24
Blocker level for Max low power gain setting BI_FL	+/- 20 MHz; BT = 0.5	typ 69 dB	24
Adjacent channel rejection at 1.5 BW for CW ACR_FL	260 kb/s, BW = 300 kHz; BT = 0.5	typ 44 dB	24
Adjacent channel rejection at 1.5 BW for CW ACR_FL	1.3 Mb/s, BW = 2.4 MHz; BT = 0.5	typ 49 dB	24
Supply currents for low power mode, demodulation running IDDRX_FSK_250_LP	BW = 300 kHz, BR = 250 kb/s; β = 0.5	typ 4.8 mA	25
Supply currents for low power mode, demodulation running IDDRX_FSK_1000_LP	BW = 1200 kHz, BR = 1000 kb/s; β = 0.5	typ 5.3 mA	25
Supply currents for low power mode, demodulation running IDDRX_FSK_2000_LP	BW = 2400 kHz, BR = 2000 kb/s; β = 0.5	typ 5.7 mA	25
Supply currents for high sensitivity mode, demodulation running IDDRX_FSK_250_HS	BW = 300 kHz, BR = 250 kb/s; β = 0.5	typ 5.5 mA	25
Supply currents for high sensitivity mode, demodulation running IDDRX_FSK_1000_HS	BW = 1200 kHz, BR = 1000 kb/s; β = 0.5	typ 6 mA	25
Supply currents for high sensitivity mode, demodulation running IDDRX_FSK_2000_HS	BW = 2400 kHz, BR = 2000 kb/s; β = 0.5	typ 6.4 mA	25
FSK Modem programmable bitrate BR_FSK	β = 0.5	min 125 · max 2000 kb/s	25
Programmable channel bandwidth range DSB BW_FSK	β = 0.5	min 300 · max 2400 kHz	25
FSK Receiver Sensitivity BER 0.1% RFS_FSK1	low power mode; 250 kb/s, β = 0.5, BW = 300 kHz	typ -96 dBm	25
FSK Receiver Sensitivity BER 0.1% RFS_FSK1	low power mode; 1 Mb/s, β = 0.5, BW = 1200 kHz	typ -92 dBm	25
FSK Receiver Sensitivity BER 0.1% RFS_FSK1_HS	high sensitivity mode; 250 kb/s, β = 0.5, BW = 300 kHz	typ -98 dBm	25
FSK Receiver Sensitivity BER 0.1% RFS_FSK1_HS	high sensitivity mode; 1 Mb/s, β = 0.5, BW = 1200 kHz	typ -94 dBm	25
FSK Receiver Sensitivity PER 1% RFS_FSK2	low power mode; 250 kb/s, β = 0.5, BW = 300 kHz	typ -93 dBm	25
FSK Receiver Sensitivity PER 1% RFS_FSK2	low power mode; 1 Mb/s, β = 0.5, BW = 1200 kHz	typ -88 dBm	25
FSK Receiver Sensitivity PER 1% RFS_FSK2_HS	high sensitivity mode; 250 kb/s, β = 0.5, BW = 300 kHz	typ -94 dBm	25
FSK Receiver Sensitivity PER 1% RFS_FSK2_HS	high sensitivity mode; 1 Mb/s, β = 0.5, BW = 1200 kHz	typ -90 dBm	25
Co-Channel Rejection CCR_FSK	β = 0.5	typ -10 dB	25
Blocker level for max low power gain setting BI_FSK	BR = 250 kb/s, BW = 300 kHz; +/- 1 MHz; β = 0.5	typ 41 dB	25
Blocker level for max low power gain setting BI_FSK	BR = 250 kb/s, BW = 300 kHz; +/- 2 MHz; β = 0.5	typ 44 dB	25
Blocker level for max low power gain setting BI_FSK	BR = 250 kb/s, BW = 300 kHz; +/- 10 MHz; β = 0.5	typ 62 dB	25
Blocker level for max low power gain setting BI_FSK	BR = 250 kb/s, BW = 300 kHz; +/- 20 MHz; β = 0.5	typ 69 dB	25
Adjacent channel rejection at 1.5 BW for CW ACR_FSK	BW = 300 kHz; β = 0.5	typ 34 dB	26
Adjacent channel rejection at 1.5 BW for CW ACR_FSK	BW = 1200 kHz; β = 0.5	typ 34 dB	26
12.5 dBm IDD_T13		typ 24 mA	26
10 dBm IDD_T10		typ 18 mA	26
0 dBm IDD_T0		typ 10 mA	26
Minimum RF output power RFOPMIN		typ -18 dBm	26
Maximum RF output power RFOPMAX		typ 12.5 dBm	26
Programmable FSK frequency deviation FDA		min 62.5 · max 1000 kHz	26
Crystal loading capacitance CLOAD		typ 10 pF	26
Crystal shunt capacitance C0XTAL		typ 2 · max 5 pF	26
Digital input level high VIH		min 0.8 VBAT_IO	27
Digital input level low VIL		max 0.2 VBAT_IO	27
Digital output level high VOH	Imax = 2.5 mA	min 0.9 VBAT_IO	27
Digital output level high VBAT_IO = 1.7 V VOH	Imax = 2.5 mA	min 0.85 VBAT_IO	27
Digital output level low VOL	Imax = -2.5 mA	max 0.1 VBAT_IO	27
Digital output level low VBAT_IO = 1.7 V VOL	Imax = -2.5 mA	max 0.12 VBAT_IO	27
Digital input leakage current ILeak	NSS, MOSI, SCK	min -1 · max 1 uA	27
NSS falling edge to SCK setup time t1	VBAT_IO = VBAT = 3.3 V; 25 °C; crystal = 52 MHz; maximum load capacitance 10 pF	min 25 ns	60
SCK period t2	VBAT_IO = VBAT = 3.3 V; 25 °C; crystal = 52 MHz; maximum load capacitance 10 pF	min 55 ns	60
SCK high time t3	VBAT_IO = VBAT = 3.3 V; 25 °C; crystal = 52 MHz; maximum load capacitance 10 pF	min 25 ns	60
MOSI to SCK hold time t4	VBAT_IO = VBAT = 3.3 V; 25 °C; crystal = 52 MHz; maximum load capacitance 10 pF	min 5 ns	60
MOSI to SCK setup time t5	VBAT_IO = VBAT = 3.3 V; 25 °C; crystal = 52 MHz; maximum load capacitance 10 pF	min 5 ns	60
NSS falling to MISO delay t6	VBAT_IO = VBAT = 3.3 V; 25 °C; crystal = 52 MHz; maximum load capacitance 10 pF	min 0 · max 15 ns	60
SCK falling to MISO delay t7	VBAT_IO = VBAT = 3.3 V; 25 °C; crystal = 52 MHz; maximum load capacitance 10 pF	min 0 · max 15 ns	60
SCK to NSS rising edge hold time t8	VBAT_IO = VBAT = 3.3 V; 25 °C; crystal = 52 MHz; maximum load capacitance 10 pF	min 25 ns	60
NSS high time t9	VBAT_IO = VBAT = 3.3 V; 25 °C; crystal = 52 MHz; maximum load capacitance 10 pF	min 100 ns	60
NSS falling edge to SCK setup time when switching from Sleep to STDBY_RC mode t10	VBAT_IO = VBAT = 3.3 V; 25 °C; crystal = 52 MHz; maximum load capacitance 10 pF	min 125 us	60
SLEEP to STDBY_RC TswMode	no data retention	typ 1200 us	70
SLEEP to STDBY_RC TswMode	with data retention	typ 130 us	70
STDBY_RC to STDBY_XOSC TswMode		typ 40 us	70
STDBY_RC to FS TswMode		typ 55 us	70
STDBY_RC to Rx TswMode		typ 85 us	70
STDBY_RC to Tx TswMode		typ 80 us	70
STDBY_XOSC to FS TswMode		typ 54 us	70
STDBY_XOSC to Tx TswMode		typ 54 us	70
STDBY_XOSC to Rx TswMode		typ 68 us	70
FS to Rx TswMode		typ 34 us	70
FS to Tx TswMode		typ 27 us	70
Rx to FS TswMode		typ 13 us	70
Rx to Tx TswMode		typ 39 us	70
Tx to FS TswMode		typ 31 us	70
Tx to Rx TswMode		typ 60 us	70
Digital output level high VBAT_IO = 1.7 V VOH	VBAT_IO = 1.7 V; Imax = 2.5 mA	min 0.85 VBAT_IO	27
Digital output level low VBAT_IO = 1.7 V VOL	VBAT_IO = 1.7 V; Imax = -2.5 mA	max 0.12 VBAT_IO	27
Digital input leakage current (NSS, MOSI, SCK) ILeak		min -1 · max 1 uA	27
NSS falling edge to SCK setup time t1	VBAT_IO = VBAT = 3.3 V, temperature = 25 °C, crystal oscillator frequency = 52 MHz; Max load cap of 10 pF	min 25 ns	60
SCK period t2	VBAT_IO = VBAT = 3.3 V, temperature = 25 °C, crystal oscillator frequency = 52 MHz; Max load cap of 10 pF	min 55 ns	60
SCK high time t3	VBAT_IO = VBAT = 3.3 V, temperature = 25 °C, crystal oscillator frequency = 52 MHz; Max load cap of 10 pF	min 25 ns	60
MOSI to SCK hold time t4	VBAT_IO = VBAT = 3.3 V, temperature = 25 °C, crystal oscillator frequency = 52 MHz; Max load cap of 10 pF	min 5 ns	60
MOSI to SCK setup time t5	VBAT_IO = VBAT = 3.3 V, temperature = 25 °C, crystal oscillator frequency = 52 MHz; Max load cap of 10 pF	min 5 ns	60
NSS falling to MISO delay t6	VBAT_IO = VBAT = 3.3 V, temperature = 25 °C, crystal oscillator frequency = 52 MHz; Max load cap of 10 pF	min 0 · max 15 ns	60
SCK falling to MISO delay t7	VBAT_IO = VBAT = 3.3 V, temperature = 25 °C, crystal oscillator frequency = 52 MHz; Max load cap of 10 pF	min 0 · max 15 ns	60
SCK to NSS rising edge hold time t8	VBAT_IO = VBAT = 3.3 V, temperature = 25 °C, crystal oscillator frequency = 52 MHz; Max load cap of 10 pF	min 25 ns	60
NSS high time t9	VBAT_IO = VBAT = 3.3 V, temperature = 25 °C, crystal oscillator frequency = 52 MHz; Max load cap of 10 pF	min 100 ns	60
NSS falling edge to SCK setup time when switching from Sleep to STDBY_RC mode t10	VBAT_IO = VBAT = 3.3 V, temperature = 25 °C, crystal oscillator frequency = 52 MHz; Max load cap of 10 pF	min 125 us	60
Junction-to-ambient thermal resistance ΘJA	QFN 24L 4X4 E-pad, 4 layers JEDEC PCB with 9 thermal vias, still air	typ 50.3 °C / W	154
Junction-to-top thermal characterization parameter ΨJT	QFN 24L 4X4 E-pad, 4 layers JEDEC PCB with 9 thermal vias, still air	typ 0.3 °C / W	154
Junction-to-case thermal resistance ΘJC	QFN 24L 4X4 E-pad, 4 layers JEDEC PCB with 9 thermal vias, still air	typ 30 °C / W	154
Junction-to-board thermal resistance ΘJB	QFN 24L 4X4 E-pad, 4 layers JEDEC PCB with 9 thermal vias, still air	typ 13.3 °C / W	154

Ordering codes, by the datasheet

SX1280IMLTRT: QFN 24 · Tape & Reel, 3’000 pieces; SX1280 includes Ranging Engine and Advanced Ranging · p. 2

Parameters

Current - Supply: 5.7mA
Current - Supply(Max): 24mA
Current Of Transmitting: 24mA
Data Rate: 2Mbps
Features: Supports RSSI function
Frequency Range: 2.4GHz~2.5GHz
Interface: UART
Junction Temperature(Max): 125℃
Operating Temperature: -40℃~+85℃
Output Power: 12.5dBm
Receive Current: 8.2mA
Sensitivity: -132dBm
Standby Current: 215nA
Thermal Resistance(Junction to Ambient): 50.3℃/W
Thermal Resistance(Junction to Board): 13.3℃/W
Thermal Resistance(Junction to Case): 30℃/W
Type: transceiver
Typical Application Frequency: 2.4GHz
Voltage - Supply: 1.8V~3.7V
Voltage - Supply(Absolute Max): 3.9V

Order codes

SX1280IMLTRTLCSC C125969

Pinout

The pins of the SX1280IMLTRT
Pin	Name	Type
1	VR_PA	Passive
2	VDD_IN	Input
3	NRESET	Input
4	XTA	Passive
5	GND	Power in
6	XTB	Passive
7	BUSY	Output
8	DIO1	Input/output
9	DIO2	Input/output
10	DIO3	Input/output
11	VBAT_IO	Input
12	DCC_FB	Output
13	GND	Power in
14	DCC_SW	Output
15	VBAT	Input
16	MISO_TX	Output
17	MOSI_RX	Input
18	SCK_RTSN	Input
19	NSS_CTS	Input
20	GND	Power in
21	GND	Power in
22	RFIO	Input/output
23	GND	Power in
24	GND	Power in
25	EP	Power in

Open-source boards using it

All 32

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BLE MIOTY MODULE
Chandubreddy819/Bluetooth-and-Mioty-Localization-Hardware
A coin-cell-powered asset-tracking module that shares a single 2.4 GHz radio (Semtech SX1280) between two protocols: frequent BLE/Google FMDN advertisements for precise short-range tracking, and periodic mioty (TS-UNB)…
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6 layers32 × 59 mm
Airbrake
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This folder contains the live KiCad project files and local component libraries:
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Dragonfly
ImShyMike/dragonfly
Tiny 3.5" FPV drone for highway
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ARES capstone with PHOBOS and DEIMOS subsystems
87 parts1

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Questions

Is there a KiCad symbol and footprint for the SX1280IMLTRT?

Yes. The symbol is Analog & Interface:SX1280IMLTRT and the footprint ICs And Semiconductors SMD:QFN50P400X400X100-25N-S265, both drawn on this page. PCBKit places them on a board for you when you design with it.

What package is the SX1280IMLTRT?

QFN-24-EP(4x4), with 25 pins. Its footprint is drawn on this page.

Where is the SX1280IMLTRT datasheet?

SEMTECH publishes it: the Datasheet link on this page opens it.

Where can I order the SX1280IMLTRT?

JLCPCB lists it as part C125969, with 3,596 in stock; the sellers' links on this page open their listings.

Which open-source boards use the SX1280IMLTRT?

32 boards in 20 repositories on GitHub; the most starred are listed on this page, with their KiCad files.