4 layers118.7 × 72.5 mm
Framework ExpansionBay IO Module
XPModder/Framework-ExpansionBay
Some stuff I made for the Framework Laptop 16 Expansion Bay
90 parts3
Overview
The FUSB303BTMX is a USB Converter made by onsemi in a X2-QFN-12(1.6x1.6) package with 12 pins. -40℃~+85℃ 2.85V~5.5V 356uA 5uA Controller USB 2.0、USB 3.1 X2-QFN-12(1.6x1.6) USB Converters ROHS.
PCBKit's library has its KiCad symbol (Interface_USB:FUSB303BTMX, from KiCad's library) and its footprint (Package_DFN_QFN:Texas_X2QFN-12_1.6x1.6mm_P0.4mm, from KiCad's library), ready for a KiCad board. 4,109 are in stock at JLCPCB (part C895444). 4 open-source boards in 4 repositories on GitHub use it.
Symbol
Footprint
From the datasheet
8- Supply, least
- 2.85 V · VDD, recommended operating min · p. 7
- Supply, most
- 5.5 V · VDD, recommended operating max · p. 7
- Supply, absolute maximum
- 6 V · VDD, absolute max · p. 7
- Works from
- -40 °C · Ambient operating min · p. 7
- Works up to
- 85 °C · Ambient operating max · p. 7
- Junction, hottest
- 150 °C · Junction absolute max · p. 7
- Takes working
- 10 µA · VDD, attached source or sink typical; excludes CC source current, 3.3 V I2C mode without AUTOSNK or accessories · p. 9
- Takes asleep
- 5 µA · VDD, disabled current max, EN_N HIGH or unconnected · p. 9
What it is and has
9- Controller
- Fully autonomous USB Type-C port controller · p. 1
- USB Type-C specification
- Release 1.3 · p. 1
- Port roles
- Source, Sink and DRP; optional accessory support · p. 1
- Preferred role modes
- Try.SRC and Try.SNK · p. 1
- Configuration
- GPIO and I2C · p. 1
- Voltage tolerance
- 28 V DC on ID, VBUS_DET, CC1 and CC2 · p. 1
- Dead battery support
- Sink role with no power applied · p. 1
- ESD protection
- 4 kV HBM for connector pins · p. 1
- Package
- 12 Lead QFN, 1.6 mm × 1.6 mm × 0.375 mm · p. 1
Around it
1- res 900 kW
- between PORT/DEBUG_N and VDD or GND; Use when strapping the port role input to reduce standby current; value reproduced as extracted. · p. 4
Specifications
87| Parameter | Conditions | As printed | Page |
|---|---|---|---|
| Supply Voltage from VDD VVDD | min -0.5 · max 6 V | 7 | |
| ID, VBUS_DET, CC1 and CC2 voltage VCON | min -0.5 · max 28 V | 7 | |
| PORT/DEBUG_N, ADDR/ORIENT, INT_N/OUT3, SDA/OUT1, SCL/OUT2 pins voltage VIO | min -0.5 · max 6 V | 7 | |
| EN_N VIO | min -0.5 · max 2 V | 7 | |
| Storage Temperature Range TSTORAGE | min -65 · max 150 C | 7 | |
| Maximum Junction Temperature TJ | max 150 C | 7 | |
| Lead Temperature (Soldering, 10 seconds) TL | max 260 C | 7 | |
| IEC 61000−4−2 System ESD with external TVS ESD | Connector Pins (VBUS, CC1 & CC2), Air Gap | min 15 kV | 7 |
| Human Body Model, JEDEC JESD22−A114 ESD | Others | min 2 kV | 7 |
| Charged Device Model, JEDEC LESD22−C101 ESD | All Pins | min 1 kV | 7 |
| VBUS_DET Voltage VBUS | min 4 · typ 5 · max 22 V | 7 | |
| Supply Voltage VDD | min 2.85 · typ 3.3 · max 5.5 V | 7 | |
| Operating Temperature TA | min -40 · max 85 C | 7 | |
| Source 80 A CC Current (Default) I80_CCX | HOST_CUR1 = 0, HOST_CUR0 = 1 or via GPIO mode | min 64 · typ 80 · max 96 A | 8 |
| Source 180 A CC Current (1.5 A) I180_CCX | HOST_CUR1 = 1, HOST_CUR0 = 0 or via GPIO mode | min 166 · typ 180 · max 194 A | 8 |
| Source 330 A CC Current (3 A) I330_CCX | HOST_CUR1 = 1, HOST_CUR0 = 1 or via GPIO mode; VDD = 3 V | min 304 · typ 330 · max 356 A | 8 |
| Sink Pull−Down Voltage in Dead Battery Under all Pull−up Source Loads VSNKDB | max 2.18 V | 8 | |
| Sink Pull−Down Resistance when VDD is within Operating Range Rd | min 4.6 · typ 5.1 · max 5.6 k | 8 | |
| CC Resistance for Disabled State zOPEN | min 126 k | 8 | |
| Ra Detection Threshold for CC Pin for Source for Default Current on VBUS vRa−SRCdef | HOST_CUR1/0 = 01 or via GPIO mode | min 0.15 · typ 0.2 · max 0.25 V | 8 |
| Ra Detection Threshold for CC Pin for Source for 1.5 A Current on VBUS vRa−SRC1.5A | HOST_CUR1/0 = 10 or via GPIO mode | min 0.35 · typ 0.4 · max 0.45 V | 8 |
| Ra Detection Threshold for CC Pin for Source for 3 A Current on VBUS vRa−SRC3A | HOST_CUR1/0 = 11 or via GPIO mode | min 0.75 · typ 0.8 · max 0.85 V | 8 |
| Rd Detection Threshold for Source for Default Current vRd−SRCdef | HOST_CUR1/0 = 01 or via GPIO mode | min 1.5 · typ 1.6 · max 1.65 V | 8 |
| Rd Detection Threshold for Source for 1.5 A Current vRd−SRC1.5A | HOST_CUR1/0 = 10 or via GPIO mode | min 1.5 · typ 1.6 · max 1.65 V | 8 |
| Rd Detection Threshold for Source for 3 A Current vRd−SRC3A | HOST_CUR1/0 = 11 or via GPIO mode; VDD = 3 V | min 2.45 · typ 2.6 · max 2.75 V | 8 |
| Ra Detection Threshold for CC Pin for Sink vRa−SNK | min 0.15 · typ 0.2 · max 0.25 V | 8 | |
| Rd Default Current Detection Threshold for Sink vRd−def | min 0.61 · typ 0.66 · max 0.7 V | 8 | |
| Rd 1.5 A Current Detection Threshold for Sink vRd−1.5A | min 1.16 · typ 1.23 · max 1.31 V | 8 | |
| Rd 3 A Current Detection Threshold for Sink vRd−3.0A | min 2.04 · typ 2.11 · max 2.18 V | 8 | |
| VBUS_DET Threshold when VBUSOK is deasserted vVBUSthr | min 2.9 · typ 3.3 · max 3.67 V | 8 | |
| VBUS_DET debounce time before VBUSOK is deasserted only tVBUSdeb | see tDeb below for VBUSOK being asserted | min 10 · max 20 ms | 8 |
| VBUS_DET Threshold when VBUSOK is asserted vVBthLH | min 3.67 · typ 4.07 · max 4.48 V | 8 | |
| VBUS_DET debounce time before VBUSOK is asserted tDeb | min 250 · max 500 s | 8 | |
| vSafe0V VBUS_DET Threshold vVSAFEthr | max 0.8 V | 8 | |
| VSAFE0V VBUS_DET Threshold hysteresis vVSAFEthrhys | typ 50 mV | 8 | |
| Leakage between VBUS and GND when VBUS not sourced rVBUSleak | min 72.4 k | 8 | |
| Effective resistance from VBUS and GND when VBUS is being discharged from vSafe5V rVBUSdschg | VDD (V) = 2.85 to 5.5 | max 2 k | 8 |
| Pull up resistor to VDD value on EN_N pin rPullup | VDD (V) = 2.85 to 5.5 | typ 6 M | 8 |
| Resistor for discharging VCONN Ra | VDD (V) = 2.85 to 5.5 | typ 1 kΩ | 8 |
| Disabled Current Idisable | VDD = 2.85 to 4.35 V; Disabled State EN N = HIGH or not connected | max 5 A | 9 |
| Unattached Sink (3.3 V I2C mode without AUTOSNK or accessories) Istby | VDD = 2.85 to 4.35 V; Nothing attached | typ 5 · max 10 A | 9 |
| Unattached DRP or Source (3.3 V I2C mode without AUTOSNK or accessories) Istby | Nothing attached, Internally Toggling | typ 10 · max 15 A | 9 |
| Attached Source or Sink (3.3 V I2C mode without AUTOSNK or accessories. Not including Ixxx_CCX current) Iattach | VDD = 2.85 to 4.35 V; Attached as a Sink or Source | typ 10 · max 15 A | 9 |
| Time a Sink port shall wait before it can determine it is detached tPDDebounce | min 10 · typ 15 · max 20 ms | 9 | |
| Time a port shall wait before it can determine it is re−attached during the try−wait process tTryCCDebounce | min 10 · max 20 ms | 9 | |
| Time a Sink port shall wait before it can determine there has been a change in Rp tRpValueChange | min 10 · max 20 ms | 9 | |
| Time a Source shall detect the SRC.Open state tSRCDisconnect | min 10 · max 20 ms | 9 | |
| Time staying in the ErrorRecovery State if sent there via the ERROR_REC bit or by a change of port roles tErrorRecovery | min 25 · typ 50 · max 100 ms | 9 | |
| Time staying in the Try.SRC/SNK prior to transition to TryWait.SRC/SNK State tDRPTry | min 75 · max 150 ms | 9 | |
| Time to discharge VBUS before giving up for cases where VBUS is always on. tTryTimeout | min 550 · max 1100 ms | 9 | |
| Time DRP shall complete transitions between Source and Sink roles tDRPTransition | min 0 · max 1 ms | 9 | |
| For DRP Operation, Time Spent in Unattached.SNK before going to Unattached.SRC State tDRPTogSNK | DRPTOGGLE = 00; default in GPIO mode | typ 70 % | 9 |
| For DRP Operation, Time Spent in Unattached.SNK before going to Unattached.SRC State tDRPTogSNK | DRPTOGGLE = 01 | typ 60 % | 9 |
| For DRP Operation, Time Spent in Unattached.SNK before going to Unattached.SRC State tDRPTogSNK | DRPTOGGLE = 10 | typ 50 % | 9 |
| For DRP Operation, Time Spent in Unattached.SNK before going to Unattached.SRC State tDRPTogSNK | DRPTOGGLE = 11 | typ 40 % | 9 |
| For DRP Operation, Time Spent in Unattached.SRC before going to Unattached.SNK State tDRPTogSRC | DRPTOGGLE = 00; default in GPIO mode | typ 30 % | 9 |
| For DRP Operation, Time Spent in Unattached.SRC before going to Unattached.SNK State tDRPTogSRC | DRPTOGGLE = 01 | typ 40 % | 9 |
| For DRP Operation, Time Spent in Unattached.SRC before going to Unattached.SNK State tDRPTogSRC | DRPTOGGLE = 10 | typ 50 % | 9 |
| For DRP Operation, Time Spent in Unattached.SRC before going to Unattached.SNK State tDRPTogSRC | DRPTOGGLE = 11 | typ 60 % | 9 |
| Time from EN_N LOW and VDD active to I2C access available tEN | VDD = 2.85 to 5.5 V | max 100 ms | 9 |
| Soft Reset Duration tRESET | VDD = 2.85 to 5.5 V | max 100 ms | 10 |
| Debounce time to detect Weak Battery VDD Threshold to trigger I_AUTOSNK if AUTOSNK mode enabled for both entering AUTOSNK and exiting AUTOSNK tAUTOSNK | VDD (V) = 2.85 to 5.5 | min 10 · typ 15 · max 20 ms | 10 |
| Output Low Voltage VOLID | ID, INT_N/OUT3; VDD = 2.85 to 5.5 V; IOL = 4 mA | max 0.4 V | 10 |
| Low−Level Input Voltage VILEN | EN_N; VDD = 2.85 to 5.5 V | max 0.4 V | 10 |
| High−Level Input Voltage VIHEN | EN_N; VDD = 2.85 to 5.5 V | min 1.2 V | 10 |
| VDD Current when EN_N is HIGH ICCTEN | VDD = 2.85 to 5.5 V; Worst Input Voltage | max 2 A | 10 |
| Impedance to VDD or GND detected as a FLOAT including when VDD = 0 Zfloat | PORT/DEBUG_N, ADDR/ORIENT; VDD = 2.85 to 5.5 V | min 1 · max 4 M | 10 |
| Low−Level Input Voltage VILI2C | SDA/OUT1, SCL/OUT2; VDD = 2.85 to 5.5 V | max 0.4 V | 10 |
| High−Level Input Voltage VIHI2C | SDA/OUT1, SCL/OUT2; VDD = 2.85 to 5.5 V | min 1.2 V | 10 |
| Hysteresis of Schmitt Trigger Inputs VHYS | SDA/OUT1, SCL/OUT2; VDD = 2.85 to 5.5 V | min 0.2 V | 10 |
| Input Current of SDA/OUT1and SCL/OUT2 Pins, Ii2C | VDD = 2.85 to 5.5 V; Input Voltage 0 V to 3.6 V | max 2 A | 10 |
| VDD Current when SDA/OUT1or SCL/OUT2 is HIGH ICCTI2C | VDD = 2.85 to 5.5 V; Worst Input Voltage | max 2 A | 10 |
| Low−Level Output Voltage at 2 mA Sink Current (Open−Drain) VOLSDA | VDD = 2.85 to 5.5 V; IOL = 2 mA | max 0.3 V | 10 |
| Low−Level Output Current (Open−Drain) IOLSDA | VDD = 3.0 to 5.5 V; VOLSDA = 0.4 V | min 20 mA | 10 |
| Capacitance for Each I/O Pin CI | VDD = 2.85 to 5.5 V | typ 5 pF | 10 |
| SCL/OUT2 Clock Frequency fSCL | Fast Mode | max 400 kHz | 11 |
| Hold Time (Repeated) START Condition tHD;STA | Fast Mode | min 0.6 s | 11 |
| Low Period of SCL/OUT2 Clock tLOW | Fast Mode | min 1.3 s | 11 |
| High Period of SCL/OUT2 Clock tHIGH | Fast Mode | min 0.6 s | 11 |
| Set−up Time for Repeated START Condition tSU;STA | Fast Mode | min 0.6 s | 11 |
| Data Hold Time tHD;DAT | Fast Mode | max 0.9 s | 11 |
| Data Set−up Time (Note 5) tSU;DAT | Fast Mode | min 100 ns | 11 |
| Rise Time of SDA/OUT1 and SCL/OUT2 Signals (Note 6) tr | Fast Mode | max 250 ns | 11 |
| Fall Time of SDA/OUT1 and SCL/OUT2 Signals (Note 6) tf | Fast Mode | max 250 ns | 11 |
| Set−up Time for STOP Condition tSU;STO | Fast Mode | min 0.6 s | 11 |
| Bus−Free Time between STOP and START Conditions tBUF | Fast Mode | min 1.3 s | 11 |
| Pulse Width of Spikes that Must Be Suppressed by the Input Filter tSP | Fast Mode | max 50 ns | 11 |
Pins, by the datasheet
12- 1 CC1
- Type−C Configuration Channel pin used for USB−C receptacles. · p. 4
- 2 CC2
- Type−C Configuration Channel pin used for USB−C receptacles. · p. 4
- 3 PORT/DEBUG_N
- Three-state input sampled at enable, power-up or soft reset: HIGH selects Source, floating selects DRP, LOW selects Sink; subsequently DEBUG_N push-pull output, LOW for Debug Accessory detected. Use a 900 kW resistor when connecting to VDD or GND to reduce standby current. · p. 4
- 4 VBUS_DET
- VBUS input pin for attach and detach detection. · p. 4
- 5 ADDR/ORIENT
- Three-state configuration input: HIGH selects I2C address 62h, floating selects GPIO mode, LOW selects I2C address 42h; subsequently ORIENT push-pull output, LOW for CC1/A5 and HIGH for CC2/B5. Use a 900 kW resistor when connecting to VDD or GND to reduce standby current. · p. 4
- 6 INT_N/OUT3
- Active LOW interrupt output in I2C mode; GPIO OUT3 is LOW when an Audio Accessory is detected and HIGH−Z otherwise. · p. 4
- 7 SDA/OUT1
- I2C SDA data signal in I2C mode; GPIO OUT1 is an input or output indicating or configuring attachment and current advertisement with ID and OUT2. · p. 4
- 8 SCL/OUT2
- I2C SCL clock signal in I2C mode; GPIO OUT2 is an input or output indicating or configuring attachment and current advertisement with ID and OUT1. · p. 4
- 9 ID
- LOW when attached as a Source; HIGH−Z when attached as a Sink. · p. 4
- 10 GND
- Ground. · p. 4
- 11 EN_N
- Active LOW device enable input with internal pull-up resistor; CONTROL1.ENABLE must also be asserted in I2C mode. · p. 4
- 12 VDD
- Input Supply Voltage. · p. 4
Ordering codes, by the datasheet
1- FUSB303BTMX
- 12−Lead Ultra−thin Molded Leadless Package (QFN) 1.6 mm x 1.6 mm x 0.375 mm · −40 to 85°C operating temperature; top mark UN; Tape and Reel · p. 17
Parameters
10- Applications Function
- Controller
- Current - Supply
- 10uA
- Features
- Low-power mode
- Junction Temperature(Max)
- 150℃
- Operating Temperature
- -40℃~+85℃
- Quiescent Supply Current
- 5uA
- Standby Current
- 5uA
- USB Protocol
- USB 3.1
- Voltage - Supply
- 2.85V~5.5V
- Voltage - Supply(Absolute Max)
- 6V
Order codes
1- FUSB303BTMXLCSC C895444
Pinout
12| Pin | Name | Type |
|---|---|---|
| 1 | CC1 | Input/output |
| 2 | CC2 | Input/output |
| 3 | PORT/DEBUG | Input/output |
| 4 | VBUS_DET | Input |
| 5 | ADDR/ORIENT | Input/output |
| 6 | INT_N/OUT3 | Open collector |
| 7 | SDA/OUT1 | Input/output |
| 8 | SCL/OUT2 | Input/output |
| 9 | ID | Open collector |
| 10 | GND | Power in |
| 11 | EN | Input |
| 12 | VDD | Power in |
Open-source boards using it
All 4- 4 layers90 × 50 mm
- 4 layers105 × 95 mm
- 4 layers75 × 50 mm
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Is there a KiCad symbol and footprint for the FUSB303BTMX?
Yes. The symbol is Interface_USB:FUSB303BTMX and the footprint Package_DFN_QFN:Texas_X2QFN-12_1.6x1.6mm_P0.4mm, both drawn on this page. PCBKit places them on a board for you when you design with it.
What package is the FUSB303BTMX?
X2-QFN-12(1.6x1.6), with 12 pins. Its footprint is drawn on this page.
Where is the FUSB303BTMX datasheet?
onsemi publishes it: the Datasheet link on this page opens it.
Where can I order the FUSB303BTMX?
JLCPCB lists it as part C895444, with 4,109 in stock; the sellers' links on this page open their listings.
What can replace the FUSB303BTMX?
Parts like it in the library: the PTN5150AHXMP by NXP Semiconductors, the TUSB320LIRWBR by Texas Instruments, the TUSB321RWBR by Texas Instruments and the TUSB320HIRWBR by Texas Instruments. Check their datasheets: a part that fits the footprint may still differ in its ratings.
Which open-source boards use the FUSB303BTMX?
4 boards in 4 repositories on GitHub; the most starred are listed on this page, with their KiCad files.
Parts like it
4
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