4 layers96 × 81 mm
PCAL6408ABSHP
NXP SemiconductorsExtended
-40℃~+85℃ 1.65V~5.5V 1uA 2 25mA 25mA 400kHz 8 I2C、SMBus Interrupt Output Push-Pull、Open-drain Reset function、Cascading and address extension、Built-in LED driver、IO level configurable HVQFN-16-EP(3x3) I/O Expanders ROHS
- Part id
- nxp/PCAL6408ABSHP
- Category
- I, O Expanders
- Package
- HVQFN-16-EP(3x3)
- Pins
- 17
- In stock
- 68 at JLCPCB (C2652332)
- Used on
- 1 open-source board
Overview
The PCAL6408ABSHP is an i, O Expander made by NXP Semiconductors in a HVQFN-16-EP(3x3) package with 17 pins. -40℃~+85℃ 1.65V~5.5V 1uA 2 25mA 25mA 400kHz 8 I2C、SMBus Interrupt Output Push-Pull、Open-drain Reset function、Cascading and address extension、Built-in LED driver、IO level configurable HVQFN-16-EP(3x3) I/O Expanders ROHS.
PCBKit's library has its KiCad symbol (Interface_Expansion:PCAL6408ABS, from KiCad's library) and its footprint (Package_DFN_QFN:VQFN-16-1EP_3x3mm_P0.5mm_EP1.6x1.6mm, from KiCad's library), ready for a KiCad board. 68 are in stock at JLCPCB (part C2652332). 1 open-source board in 1 repository on GitHub use it.
Symbol
Footprint
From the datasheet
16- Supply, least
- 1.65 V · VDD(I2C-bus), recommended operating min · p. 22
- Supply, most
- 5.5 V · VDD(I2C-bus), recommended operating max · p. 22
- Supply, absolute maximum
- 6.5 V · VDD(I2C-bus), absolute max · p. 22
- Works from
- -40 °C · Ambient operating in free air min · p. 22
- Works up to
- 85 °C · Ambient operating in free air max · p. 22
- Takes working
- 10 µA · sum of IDD(I2C-bus) and IDD(P), operating typical, 400 kHz, VDD(P) = 3.6–5.5 V · p. 24
- Takes working
- 6.5 µA · sum of IDD(I2C-bus) and IDD(P), operating typical, 400 kHz, VDD(P) = 2.3–3.6 V · p. 24
- Takes working
- 4 µA · sum of IDD(I2C-bus) and IDD(P), operating typical, 400 kHz, VDD(P) = 1.65–2.3 V · p. 24
- Takes at most
- 125 µA · sum of IDD(I2C-bus) and IDD(P), active continuous register read max, 400 kHz, VDD(P) = 3.6–5.5 V · p. 24
- Takes asleep
- 1.5 µA · sum of IDD(I2C-bus) and IDD(P), standby typical, VDD(P) = 3.6–5.5 V · p. 24
- Takes asleep
- 1 µA · sum of IDD(I2C-bus) and IDD(P), standby typical, VDD(P) = 2.3–3.6 V · p. 24
- Takes asleep
- 500 nA · sum of IDD(I2C-bus) and IDD(P), standby typical, VDD(P) = 1.65–2.3 V · p. 24
- A pin gives at most
- 50 mA · P port continuous LOW-level output current absolute max · p. 22
- A pin gives at most
- 25 mA · P port continuous HIGH-level output current absolute max · p. 22
- Data rate, most
- 400 kbit/s · Fast-mode I2C bus clock max · p. 29
- Takes at most
- 750 µA · sum of IDD(I2C-bus) and IDD(P), max with pullups enabled and P port LOW · p. 25
What it is and has
17- GPIO
- 8-bit general-purpose I/O expander · p. 2
- Voltage translation
- Bidirectional voltage-level translation and GPIO expansion · p. 3
- I/O tolerance
- 5 V tolerant I/O ports · p. 3
- Reset
- Active LOW reset input · p. 3
- Interrupt
- Open-drain active LOW interrupt output · p. 3
- Power-on reset
- Internal · p. 3
- Power-up configuration
- All channels configured as inputs · p. 3
- Input filtering
- Noise filter on SCL/SDA · p. 3
- Output drive
- Latched outputs, 25 mA maximum drive capability · p. 3
- ESD protection
- 2000 V human-body model (A114-A) · p. 3
- ESD protection
- 1000 V charged-device model (C101) · p. 3
- Latch-up performance
- Exceeds 100 mA per JESD 78, Class II · p. 3
- Output configuration
- Bank selectable push-pull or open-drain · p. 3
- Interrupt status
- Read-only register identifies interrupt source · p. 3
- Input latch
- Input values retained until Input port register is read · p. 3
- Internal pullup/pulldown
- Selectable 100 kΩ · p. 3
- Package
- HVQFN16, 3 × 3 × 0.85 mm · p. 4
Around it
4- res not specified
- between RESET and VDD(I2C-bus); Pullup required if no active connection is used. · p. 14
- res not specified
- between INT and VDD(I2C-bus); Interrupt output pullup. · p. 7
- res not specified
- between SCL and VDD(I2C-bus); Serial clock bus pullup. · p. 8
- res not specified
- between SDA and VDD(I2C-bus); Serial data bus pullup. · p. 8
Specifications
163| Parameter | Conditions | As printed | Page |
|---|---|---|---|
| I C-bus supply voltage VDD(I2C-bus) | min -0.5 · max 6.5 V | 22 | |
| Supply voltage port P VDD(P) | min -0.5 · max 6.5 V | 22 | |
| Input voltage VI | Note [1] | min -0.5 · max 6.5 V | 22 |
| Output voltage VO | Note [1] | min -0.5 · max 6.5 V | 22 |
| LOW-level output current IOL | Continuous; P port; VO = 0 V to VDD(P) | max 50 mA | 22 |
| LOW-level output current IOL | Continuous; SDA, INT; VO = 0 V to VDD(I2C-bus) | max 25 mA | 22 |
| HIGH-level output current IOH | Continuous; P port; VO = 0 V to VDD(P) | max 25 mA | 22 |
| Supply current IDD | Continuous through VSS | max 200 mA | 22 |
| Supply current port P IDD(P) | Continuous through VDD(P) | max 160 mA | 22 |
| I C-bus supply current IDD(I2C-bus) | Continuous through VDD(I2C-bus) | max 10 mA | 22 |
| Storage temperature Tstg | min -65 · max 150 °C | 22 | |
| I C-bus supply voltage VDD(I2C-bus) | min 1.65 · max 5.5 V | 22 | |
| Supply voltage port P VDD(P) | min 1.65 · max 5.5 V | 22 | |
| HIGH-level input voltage VIH | SCL, SDA, and RESET | max 5.5 V | 22 |
| HIGH-level input voltage VIH | ADDR and P7 to P0 | max 5.5 V | 22 |
| LOW-level input voltage VIL | SCL, SDA, and RESET | min -0.5 V | 22 |
| LOW-level input voltage VIL | ADDR and P7 to P0 | min -0.5 V | 22 |
| HIGH-level output current IOH | P7 to P0 | max 10 mA | 22 |
| LOW-level output current IOL | P7 to P0 | max 25 mA | 22 |
| Ambient temperature Tamb | Operating in free air | min -40 · max 85 °C | 22 |
| Transient thermal impedance from junction to ambient Zth(j-a) | HVQFN16 package; calculated in accordance with JESD 51-7 | max 53 K/W | 23 |
| Input clamping voltage VIK | II = -18 mA; VDD(P) = 1.65 V to 5.5 V | min -1.2 V | 23 |
| Power-on reset voltage VPOR | VI = VDD(P) or VSS; IO = 0 mA; VDD(P) = 1.65 V to 5.5 V | typ 1 · max 1.4 V | 23 |
| HIGH-level output voltage VOH | P port; IOH = -8 mA; CCX = 11b; VDD(P) = 1.65 V | min 1.2 V | 23 |
| HIGH-level output voltage VOH | P port; IOH = -8 mA; CCX = 11b; VDD(P) = 2.3 V | min 1.8 V | 23 |
| HIGH-level output voltage VOH | P port; IOH = -8 mA; CCX = 11b; VDD(P) = 3 V | min 2.6 V | 23 |
| HIGH-level output voltage VOH | P port; IOH = -8 mA; CCX = 11b; VDD(P) = 4.5 V | min 4.1 V | 23 |
| HIGH-level output voltage VOH | P port; IOH = -2.5 mA and CCX = 00b; IOH = -5 mA and CCX = 01b; IOH = -7.5 mA and CCX = 10b; IOH = -10 mA and CCX = 11b; VDD(P) = 1.65 V | min 1.1 V | 23 |
| HIGH-level output voltage VOH | P port; IOH = -2.5 mA and CCX = 00b; IOH = -5 mA and CCX = 01b; IOH = -7.5 mA and CCX = 10b; IOH = -10 mA and CCX = 11b; VDD(P) = 2.3 V | min 1.7 V | 23 |
| HIGH-level output voltage VOH | P port; IOH = -2.5 mA and CCX = 00b; IOH = -5 mA and CCX = 01b; IOH = -7.5 mA and CCX = 10b; IOH = -10 mA and CCX = 11b; VDD(P) = 3 V | min 2.5 V | 23 |
| HIGH-level output voltage VOH | P port; IOH = -2.5 mA and CCX = 00b; IOH = -5 mA and CCX = 01b; IOH = -7.5 mA and CCX = 10b; IOH = -10 mA and CCX = 11b; VDD(P) = 4.5 V | min 4 V | 23 |
| LOW-level output voltage VOL | P port; IOL = 8 mA; CCX = 11b; VDD(P) = 1.65 V | max 0.45 V | 23 |
| LOW-level output voltage VOL | P port; IOL = 8 mA; CCX = 11b; VDD(P) = 2.3 V | max 0.25 V | 23 |
| LOW-level output voltage VOL | P port; IOL = 8 mA; CCX = 11b; VDD(P) = 3 V | max 0.25 V | 23 |
| LOW-level output voltage VOL | P port; IOL = 8 mA; CCX = 11b; VDD(P) = 4.5 V | max 0.2 V | 23 |
| LOW-level output voltage VOL | P port; IOL = 2.5 mA and CCX = 00b; IOL = 5 mA and CCX = 01b; IOL = 7.5 mA and CCX = 10b; IOL = 10 mA and CCX = 11b; VDD(P) = 1.65 V | max 0.5 V | 23 |
| LOW-level output voltage VOL | P port; IOL = 2.5 mA and CCX = 00b; IOL = 5 mA and CCX = 01b; IOL = 7.5 mA and CCX = 10b; IOL = 10 mA and CCX = 11b; VDD(P) = 2.3 V | max 0.3 V | 23 |
| LOW-level output voltage VOL | P port; IOL = 2.5 mA and CCX = 00b; IOL = 5 mA and CCX = 01b; IOL = 7.5 mA and CCX = 10b; IOL = 10 mA and CCX = 11b; VDD(P) = 3 V | max 0.25 V | 24 |
| LOW-level output voltage VOL | P port; IOL = 2.5 mA and CCX = 00b; IOL = 5 mA and CCX = 01b; IOL = 7.5 mA and CCX = 10b; IOL = 10 mA and CCX = 11b; VDD(P) = 4.5 V | max 0.2 V | 24 |
| LOW-level output current IOL | SDA; VOL = 0.4 V; VDD(P) = 1.65 V to 5.5 V | min 3 mA | 24 |
| LOW-level output current IOL | INT; VOL = 0.4 V; VDD(P) = 1.65 V to 5.5 V; typical at Tamb = 25 °C, VDD = 3.3 V; for VDD < 2.5 V, typical at VOL = 0.6 V | min 3 · typ 15 mA | 24 |
| HIGH-level input current IIH | P port; VI = VDD(P); VDD(P) = 1.65 V to 5.5 V | max 1 uA | 24 |
| LOW-level input current IIL | P port; VI = VSS; VDD(P) = 1.65 V to 5.5 V | max 1 uA | 24 |
| Supply current IDD | IDD(I2C-bus) + IDD(P); Operating mode; SDA, P port, ADDR, RESET; VI on SDA and RESET = VDD(I2C-bus) or VSS; VI on P port and ADDR = VDD(P) or VSS; IO = 0 mA; I/O = inputs; fSCL = 400 kHz; VDD(P) = 3.6 V to 5.5 V | typ 10 · max 25 uA | 24 |
| Supply current IDD | IDD(I2C-bus) + IDD(P); Operating mode; SDA, P port, ADDR, RESET; VI on SDA and RESET = VDD(I2C-bus) or VSS; VI on P port and ADDR = VDD(P) or VSS; IO = 0 mA; I/O = inputs; fSCL = 400 kHz; VDD(P) = 2.3 V to 3.6 V | typ 6.5 · max 15 uA | 24 |
| Supply current IDD | IDD(I2C-bus) + IDD(P); Operating mode; SDA, P port, ADDR, RESET; VI on SDA and RESET = VDD(I2C-bus) or VSS; VI on P port and ADDR = VDD(P) or VSS; IO = 0 mA; I/O = inputs; fSCL = 400 kHz; VDD(P) = 1.65 V to 2.3 V | typ 4 · max 9 uA | 24 |
| Supply current IDD | IDD(I2C-bus) + IDD(P); Standby mode; SCL, SDA, P port, ADDR, RESET; VI on SCL, SDA, and RESET = VDD(I2C-bus) or VSS; VI on P port and ADDR = VDD(P); IO = 0 mA; I/O = inputs; fSCL = 0 kHz; VDD(P) = 3.6 V to 5.5 V | typ 1.5 · max 7 uA | 24 |
| Supply current IDD | IDD(I2C-bus) + IDD(P); Standby mode; SCL, SDA, P port, ADDR, RESET; VI on SCL, SDA, and RESET = VDD(I2C-bus) or VSS; VI on P port and ADDR = VDD(P); IO = 0 mA; I/O = inputs; fSCL = 0 kHz; VDD(P) = 2.3 V to 3.6 V | typ 1 · max 3.2 uA | 24 |
| Supply current IDD | IDD(I2C-bus) + IDD(P); Standby mode; SCL, SDA, P port, ADDR, RESET; VI on SCL, SDA, and RESET = VDD(I2C-bus) or VSS; VI on P port and ADDR = VDD(P); IO = 0 mA; I/O = inputs; fSCL = 0 kHz; VDD(P) = 1.65 V to 2.3 V | typ 0.5 · max 1.7 uA | 24 |
| Supply current IDD | Active mode; IDD(I2C-bus) + IDD(P); P port, ADDR, RESET; VI on RESET = VDD(I2C-bus); VI on P port and ADDR = VDD(P); IO = 0 mA; I/O = inputs; fSCL = 400 kHz, continuous register read; VDD(P) = 3.6 V to 5.5 V | typ 60 · max 125 uA | 24 |
| Supply current IDD | Active mode; IDD(I2C-bus) + IDD(P); P port, ADDR, RESET; VI on RESET = VDD(I2C-bus); VI on P port and ADDR = VDD(P); IO = 0 mA; I/O = inputs; fSCL = 400 kHz, continuous register read; VDD(P) = 2.3 V to 3.6 V | typ 40 · max 75 uA | 24 |
| Supply current IDD | Active mode; IDD(I2C-bus) + IDD(P); P port, ADDR, RESET; VI on RESET = VDD(I2C-bus); VI on P port and ADDR = VDD(P); IO = 0 mA; I/O = inputs; fSCL = 400 kHz, continuous register read; VDD(P) = 1.65 V to 2.3 V | typ 20 · max 45 uA | 24 |
| Supply current IDD | With pullups enabled; IDD(I2C-bus) + IDD(P); P port, ADDR, RESET; VI on SCL, SDA, and RESET = VDD(I2C-bus) or VSS; VI on P port = VSS; VI on ADDR = VDD(I2C-bus) or VSS; IO = 0 mA; I/O = inputs with pullup enabled; fSCL = 0 kHz; VDD(P) = 1.65 V to 5.5 V | typ 0.55 · max 0.75 mA | 25 |
| Additional quiescent supply current ΔIDD | SCL, SDA, RESET; One input at VDD(I2C-bus) - 0.6 V, Other inputs at VDD(I2C-bus) or VSS; VDD(P) = 1.65 V to 5.5 V; internal pullup/pulldown resistor disabled | max 25 uA | 25 |
| Additional quiescent supply current ΔIDD | P port and ADDR; One input at VDD(P) - 0.6 V, Other inputs at VDD(P) or VSS; VDD(P) = 1.65 V to 5.5 V; internal pullup/pulldown resistor disabled | max 80 uA | 25 |
| Input capacitance Ci | SCL; VI = VDD(I2C-bus) or VSS; VDD(P) = 1.65 V to 5.5 V | typ 6 · max 7 pF | 25 |
| Input/output capacitance Cio | SDA; VI/O = VDD(I2C-bus) or VSS; VDD(P) = 1.65 V to 5.5 V | typ 7 · max 8 pF | 25 |
| Input/output capacitance Cio | P port; VI/O = VDD(P) or VSS; VDD(P) = 1.65 V to 5.5 V | typ 7.5 · max 8.5 pF | 25 |
| Internal pullup resistance Rpu(int) | Input/output | min 50 · typ 100 · max 150 kΩ | 25 |
| Internal pulldown resistance Rpd(int) | Input/output | min 50 · typ 100 · max 150 kΩ | 25 |
| SCL clock frequency fSCL | Standard-mode I C-bus | min 0 · max 100 kHz | 29 |
| SCL clock frequency fSCL | Fast-mode I C-bus | min 0 · max 400 kHz | 29 |
| HIGH period of the SCL clock tHIGH | Standard-mode I C-bus | min 4 us | 29 |
| HIGH period of the SCL clock tHIGH | Fast-mode I C-bus | min 0.6 us | 29 |
| LOW period of the SCL clock tLOW | Standard-mode I C-bus | min 4.7 us | 29 |
| LOW period of the SCL clock tLOW | Fast-mode I C-bus | min 1.3 us | 29 |
| Pulse width of spikes that must be suppressed by the input filter tSP | Standard-mode I C-bus | min 0 · max 50 ns | 29 |
| Pulse width of spikes that must be suppressed by the input filter tSP | Fast-mode I C-bus | min 0 · max 50 ns | 29 |
| Data set-up time tSU;DAT | Standard-mode I C-bus | min 250 ns | 30 |
| Data set-up time tSU;DAT | Fast-mode I C-bus | min 100 ns | 30 |
| Data hold time tHD;DAT | Standard-mode I C-bus | min 0 ns | 30 |
| Data hold time tHD;DAT | Fast-mode I C-bus | min 0 ns | 30 |
| Rise time of both SDA and SCL signals tr | Standard-mode I C-bus | max 1000 ns | 30 |
| Rise time of both SDA and SCL signals tr | Fast-mode I C-bus | min 20 · max 300 ns | 30 |
| Fall time of both SDA and SCL signals tf | Standard-mode I C-bus | max 300 ns | 30 |
| Fall time of both SDA and SCL signals tf | Fast-mode I C-bus; minimum = 20 × (VDD / 5.5 V) ns | max 300 ns | 30 |
| Bus free time between a STOP and START condition tBUF | Standard-mode I C-bus | min 4.7 us | 30 |
| Bus free time between a STOP and START condition tBUF | Fast-mode I C-bus | min 1.3 us | 30 |
| Set-up time for a repeated START condition tSU;STA | Standard-mode I C-bus | min 4.7 us | 30 |
| Set-up time for a repeated START condition tSU;STA | Fast-mode I C-bus | min 0.6 us | 30 |
| Hold time (repeated) START condition tHD;STA | Standard-mode I C-bus | min 4 us | 30 |
| Hold time (repeated) START condition tHD;STA | Fast-mode I C-bus | min 0.6 us | 30 |
| Set-up time for STOP condition tSU;STO | Standard-mode I C-bus | min 4 us | 30 |
| Set-up time for STOP condition tSU;STO | Fast-mode I C-bus | min 0.6 us | 30 |
| Data valid time tVD;DAT | Standard-mode I C-bus; SCL LOW to SDA output valid | max 3.45 us | 30 |
| Data valid time tVD;DAT | Fast-mode I C-bus; SCL LOW to SDA output valid | max 0.9 us | 30 |
| Data valid acknowledge time tVD;ACK | Standard-mode I C-bus; ACK signal from SCL LOW to SDA (out) LOW | max 3.45 us | 30 |
| Data valid acknowledge time tVD;ACK | Fast-mode I C-bus; ACK signal from SCL LOW to SDA (out) LOW | max 0.9 us | 30 |
| Reset pulse width tw(rst) | Standard-mode I C-bus | min 30 ns | 30 |
| Reset pulse width tw(rst) | Fast-mode I C-bus | min 30 ns | 30 |
| Reset recovery time trec(rst) | Standard-mode I C-bus | min 200 ns | 30 |
| Reset recovery time trec(rst) | Fast-mode I C-bus | min 200 ns | 30 |
| Reset time trst | Standard-mode I C-bus; minimum time for SDA to become HIGH or minimum time to wait before doing a START | min 600 ns | 30 |
| Reset time trst | Fast-mode I C-bus; minimum time for SDA to become HIGH or minimum time to wait before doing a START | min 600 ns | 30 |
| Valid time on pin INT tv(INT) | Standard-mode I C-bus; From P port to INT; CL ≤ 100 pF | max 1 us | 30 |
| Valid time on pin INT tv(INT) | Fast-mode I C-bus; From P port to INT; CL ≤ 100 pF | max 1 us | 30 |
| Reset time on pin INT trst(INT) | Standard-mode I C-bus; From SCL to INT; CL ≤ 100 pF | max 1 us | 30 |
| Reset time on pin INT trst(INT) | Fast-mode I C-bus; From SCL to INT; CL ≤ 100 pF | max 1 us | 30 |
| Data output valid time tv(Q) | Standard-mode I C-bus; From SCL to P port; CL ≤ 100 pF | max 400 ns | 30 |
| Data output valid time tv(Q) | Fast-mode I C-bus; From SCL to P port; CL ≤ 100 pF | max 400 ns | 30 |
| Data input set-up time tsu(D) | Standard-mode I C-bus; From P port to SCL; CL ≤ 100 pF | min 0 ns | 30 |
| Data input set-up time tsu(D) | Fast-mode I C-bus; From P port to SCL; CL ≤ 100 pF | min 0 ns | 30 |
| Data input hold time th(D) | Standard-mode I C-bus; From P port to SCL; CL ≤ 100 pF | min 300 ns | 31 |
| Data input hold time th(D) | Fast-mode I C-bus; From P port to SCL; CL ≤ 100 pF | min 300 ns | 31 |
| Input voltage VI | The input negative-voltage rating can be exceeded if the input current rating is observed. | min -0.5 · max 6.5 V | 22 |
| Output voltage VO | The output voltage rating can be exceeded if the output current rating is observed. | min -0.5 · max 6.5 V | 22 |
| Input clamping current IIK | ADDR, RESET, and SCL; VI < 0 V; maximum magnitude ±20 mA | max 20 mA | 22 |
| Output clamping current IOK | INT; VO < 0 V; maximum magnitude ±20 mA | max 20 mA | 22 |
| Input/output clamping current IIOK | P port; VO < 0 V or VO > VDD(P); maximum magnitude ±20 mA | max 20 mA | 22 |
| Input/output clamping current IIOK | SDA; VO < 0 V or VO > VDD(I2C-bus); maximum magnitude ±20 mA | max 20 mA | 22 |
| HIGH-level input voltage VIH | SCL, SDA, and RESET; minimum = 0.7 × VDD(I2C-bus) | max 5.5 V | 22 |
| HIGH-level input voltage VIH | ADDR and P7 to P0; minimum = 0.7 × VDD(P) | max 5.5 V | 22 |
| LOW-level input voltage VIL | SCL, SDA, and RESET; maximum = 0.3 × VDD(I2C-bus) | min -0.5 V | 22 |
| LOW-level input voltage VIL | ADDR and P7 to P0; maximum = 0.3 × VDD(P) | min -0.5 V | 22 |
| LOW-level output current IOL | INT; VOL = 0.4 V; VDD(P) = 1.65 V to 5.5 V. Typical at Tamb = 25 °C, VOL = 0.4 V and VDD = 3.3 V; for VDD < 2.5 V, VOL = 0.6 V. | min 3 · typ 15 mA | 24 |
| Input current II | VDD(P) = 1.65 V to 5.5 V; SCL, SDA, RESET; VI = VDD(I2C-bus) or VSS; maximum magnitude ±1 uA | max 1 uA | 24 |
| Input current II | VDD(P) = 1.65 V to 5.5 V; ADDR; VI = VDD(P) or VSS; maximum magnitude ±1 uA | max 1 uA | 24 |
| Additional quiescent supply current ΔIDD | SCL, SDA, RESET; One input at VDD(I2C-bus) - 0.6 V; Other inputs at VDD(I2C-bus) or VSS; VDD(P) = 1.65 V to 5.5 V; internal pullup/pulldown resistor disabled | max 25 uA | 25 |
| Additional quiescent supply current ΔIDD | P port and ADDR; One input at VDD(P) - 0.6 V; Other inputs at VDD(P) or VSS; VDD(P) = 1.65 V to 5.5 V; internal pullup/pulldown resistor disabled | max 80 uA | 25 |
| SCL clock frequency fSCL | Standard-mode I C-bus; over recommended operating free air temperature range | min 0 · max 100 kHz | 29 |
| SCL clock frequency fSCL | Fast-mode I C-bus; over recommended operating free air temperature range | min 0 · max 400 kHz | 29 |
| HIGH period of the SCL clock tHIGH | Standard-mode I C-bus; over recommended operating free air temperature range | min 4 us | 29 |
| HIGH period of the SCL clock tHIGH | Fast-mode I C-bus; over recommended operating free air temperature range | min 0.6 us | 29 |
| LOW period of the SCL clock tLOW | Standard-mode I C-bus; over recommended operating free air temperature range | min 4.7 us | 29 |
| LOW period of the SCL clock tLOW | Fast-mode I C-bus; over recommended operating free air temperature range | min 1.3 us | 29 |
| Pulse width of spikes that must be suppressed by the input filter tSP | Standard-mode I C-bus; over recommended operating free air temperature range | min 0 · max 50 ns | 29 |
| Pulse width of spikes that must be suppressed by the input filter tSP | Fast-mode I C-bus; over recommended operating free air temperature range | min 0 · max 50 ns | 29 |
| Data set-up time tSU;DAT | Standard-mode I C-bus; over recommended operating free air temperature range | min 250 ns | 30 |
| Data set-up time tSU;DAT | Fast-mode I C-bus; over recommended operating free air temperature range | min 100 ns | 30 |
| Data hold time tHD;DAT | Standard-mode I C-bus; over recommended operating free air temperature range | min 0 ns | 30 |
| Data hold time tHD;DAT | Fast-mode I C-bus; over recommended operating free air temperature range | min 0 ns | 30 |
| Rise time of both SDA and SCL signals tr | Standard-mode I C-bus; over recommended operating free air temperature range | max 1000 ns | 30 |
| Rise time of both SDA and SCL signals tr | Fast-mode I C-bus; over recommended operating free air temperature range | min 20 · max 300 ns | 30 |
| Fall time of both SDA and SCL signals tf | Standard-mode I C-bus; over recommended operating free air temperature range | max 300 ns | 30 |
| Fall time of both SDA and SCL signals tf | Fast-mode I C-bus; minimum = 20 × (VDD / 5.5 V) ns; over recommended operating free air temperature range | max 300 ns | 30 |
| Bus free time between a STOP and START condition tBUF | Standard-mode I C-bus; over recommended operating free air temperature range | min 4.7 us | 30 |
| Bus free time between a STOP and START condition tBUF | Fast-mode I C-bus; over recommended operating free air temperature range | min 1.3 us | 30 |
| Set-up time for a repeated START condition tSU;STA | Standard-mode I C-bus; over recommended operating free air temperature range | min 4.7 us | 30 |
| Set-up time for a repeated START condition tSU;STA | Fast-mode I C-bus; over recommended operating free air temperature range | min 0.6 us | 30 |
| Hold time (repeated) START condition tHD;STA | Standard-mode I C-bus; over recommended operating free air temperature range | min 4 us | 30 |
| Hold time (repeated) START condition tHD;STA | Fast-mode I C-bus; over recommended operating free air temperature range | min 0.6 us | 30 |
| Set-up time for STOP condition tSU;STO | Standard-mode I C-bus; over recommended operating free air temperature range | min 4 us | 30 |
| Set-up time for STOP condition tSU;STO | Fast-mode I C-bus; over recommended operating free air temperature range | min 0.6 us | 30 |
| Data valid time tVD;DAT | Standard-mode I C-bus; SCL LOW to SDA output valid; over recommended operating free air temperature range | max 3.45 us | 30 |
| Data valid time tVD;DAT | Fast-mode I C-bus; SCL LOW to SDA output valid; over recommended operating free air temperature range | max 0.9 us | 30 |
| Data valid acknowledge time tVD;ACK | Standard-mode I C-bus; ACK signal from SCL LOW to SDA (out) LOW; over recommended operating free air temperature range | max 3.45 us | 30 |
| Data valid acknowledge time tVD;ACK | Fast-mode I C-bus; ACK signal from SCL LOW to SDA (out) LOW; over recommended operating free air temperature range | max 0.9 us | 30 |
| Reset pulse width tw(rst) | Standard-mode I C-bus; over recommended operating free air temperature range | min 30 ns | 30 |
| Reset pulse width tw(rst) | Fast-mode I C-bus; over recommended operating free air temperature range | min 30 ns | 30 |
| Reset recovery time trec(rst) | Standard-mode I C-bus; over recommended operating free air temperature range | min 200 ns | 30 |
| Reset recovery time trec(rst) | Fast-mode I C-bus; over recommended operating free air temperature range | min 200 ns | 30 |
| Reset time trst | Standard-mode I C-bus; minimum time for SDA to become HIGH or minimum time to wait before doing a START; over recommended operating free air temperature range | min 600 ns | 30 |
| Reset time trst | Fast-mode I C-bus; minimum time for SDA to become HIGH or minimum time to wait before doing a START; over recommended operating free air temperature range | min 600 ns | 30 |
| Valid time on pin INT tv(INT) | Standard-mode I C-bus; From P port to INT; CL ≤ 100 pF; over recommended operating free air temperature range | max 1 us | 30 |
| Valid time on pin INT tv(INT) | Fast-mode I C-bus; From P port to INT; CL ≤ 100 pF; over recommended operating free air temperature range | max 1 us | 30 |
| Reset time on pin INT trst(INT) | Standard-mode I C-bus; From SCL to INT; CL ≤ 100 pF; over recommended operating free air temperature range | max 1 us | 30 |
| Reset time on pin INT trst(INT) | Fast-mode I C-bus; From SCL to INT; CL ≤ 100 pF; over recommended operating free air temperature range | max 1 us | 30 |
| Data output valid time tv(Q) | Standard-mode I C-bus; From SCL to P port; CL ≤ 100 pF; over recommended operating free air temperature range | max 400 ns | 30 |
| Data output valid time tv(Q) | Fast-mode I C-bus; From SCL to P port; CL ≤ 100 pF; over recommended operating free air temperature range | max 400 ns | 30 |
| Data input set-up time tsu(D) | Standard-mode I C-bus; From P port to SCL; CL ≤ 100 pF; over recommended operating free air temperature range | min 0 ns | 30 |
| Data input set-up time tsu(D) | Fast-mode I C-bus; From P port to SCL; CL ≤ 100 pF; over recommended operating free air temperature range | min 0 ns | 30 |
| Data input hold time th(D) | Standard-mode I C-bus; From P port to SCL; CL ≤ 100 pF; over recommended operating free air temperature range | min 300 ns | 31 |
| Data input hold time th(D) | Fast-mode I C-bus; From P port to SCL; CL ≤ 100 pF; over recommended operating free air temperature range | min 300 ns | 31 |
Pins, by the datasheet
16- 1 RESET
- Active LOW reset input; connect to VDD(I2C-bus) through a pullup resistor if no active connection is used. · p. 7
- 2 P0
- Port P input/output 0. · p. 7
- 3 P1
- Port P input/output 1. · p. 7
- 4 P2
- Port P input/output 2. · p. 7
- 5 P3
- Port P input/output 3. · p. 7
- 6 VSS
- Ground. · p. 7
- 7 P4
- Port P input/output 4. · p. 7
- 8 P5
- Port P input/output 5. · p. 7
- 9 P6
- Port P input/output 6. · p. 7
- 10 P7
- Port P input/output 7. · p. 7
- 11 INT
- Active LOW interrupt output; connect to VDD(I2C-bus) through a pullup resistor. · p. 7
- 12 SCL
- Serial clock bus; connect to VDD(I2C-bus) through a pullup resistor. · p. 8
- 13 SDA
- Serial data bus; connect to VDD(I2C-bus) through a pullup resistor. · p. 8
- 14 VDD(P)
- Supply voltage of PCAL6408A for Port P. · p. 8
- 15 VDD(I2C-bus)
- I2C-bus supply; connect directly to the external I2C controller VDD; provides voltage-level translation. · p. 7
- 16 ADDR
- Address input; connect directly to VDD(P) or ground. · p. 7
Ordering codes, by the datasheet
5- PCAL6408ABSHP
- HVQFN16 · Reel 13" Q2/T3; minimum order 6000; Tamb = -40 °C to +85 °C · p. 4
- PCAL6408APWJ
- TSSOP16 · Reel 13" Q1/T1; minimum order 2500; Tamb = -40 °C to +85 °C · p. 4
- PCAL6408AHKX
- XQFN16 · Reel 7" Q1/T1; minimum order 4000; Tamb = -40 °C to +85 °C · p. 4
- PCAL6408AEXX
- XFBGA16 · Reel 7" Q1/T1; minimum order 5000; Tamb = -40 °C to +85 °C; discontinued with lifetime buy November 2016 · p. 4
- PCAL6408AEX1Z
- X2QFN16 · Reel 7" Q2/T1; minimum order 5000; Tamb = -40 °C to +85 °C · p. 4
Open-source boards using it
1Parts like it
8
PCA9539DBR
SSOP-24-208mil-40℃~+85℃ 10mA 16 1uA 2.3V~5.5V 25mA 4 400kHz I2C、SMBus Interrupt Output Push-Pull Reset function、Cascade and address expansion、Built-in LED driver SSOP-24-208mil I/O Expanders ROHSTexas InstrumentsI/O Expanders
PCA9538ABSHP
QFN-16-EP(3x3)-40℃~+85℃ 1.65V~5.5V 400kHz 8 I2C、SMBus Interrupt Output Reset function、Cascading and address extension、Built-in LED driver QFN-16-EP(3x3) I/O Expanders ROHSNXP SemiconductorsI/O Expanders
PCF8575DGVR
TVSOP-24-4.4mm-40℃~+85℃ 2.5V~5.5V 25mA 300uA 400kHz 8 I2C、SMBus Interrupt Output Reset function、Cascade and address expansion、Built-in LED driver TVSOP-24-4.4mm I/O Expanders ROHSTexas InstrumentsI/O Expanders
TPT29548A-QF8R
QFN-24Reset function、Cascading and address extension、IO level configurable QFN-24(4x4) I/O Expanders ROHS3PEAKI/O Expanders
PCA9534ARGT
VQFN-16-EP(3x3)-40℃~+85℃ 10mA 1uA 2.3V~5.5V 25mA 400kHz 4V 700mV 8 8 I2C、SMBus Interrupt Output Push-Pull Reset function、Cascading and address extension、Built-in LED driver VQFN-16-EP(3x3) I/O Expanders ROHSTexas InstrumentsI/O Expanders
MAX7323AEE+
QSOP-16-150mil-40℃~+125℃ 1.71V~5.5V 400kHz 8 I2C Interrupt Output Push-Pull、Open-drain Reset function、Cascade and address expansion、Built-in LED driver、IO level configurable QSOP-16-150mil I/O Expanders ROHSMaxim Integrated (Analog Devices)I/O Expanders
TCA9554ADB
SSOP-16-208mil-40℃~+85℃ 1.65V~5.5V 400kHz 8 I2C、SMBus Interrupt Output Open-drain Reset function、Cascading and address extension、Built-in LED driver SSOP-16-208mil I/O Expanders ROHSTexas InstrumentsI/O ExpandersMAX7311AAG+
SSOP-24-208milReset function、Cascading and address extension SSOP-24-208mil I/O Expanders ROHSMaxim Integrated (Analog Devices)I/O Expanders
Questions
Is there a KiCad symbol and footprint for the PCAL6408ABSHP?
Yes. The symbol is Interface_Expansion:PCAL6408ABS and the footprint Package_DFN_QFN:VQFN-16-1EP_3x3mm_P0.5mm_EP1.6x1.6mm, both drawn on this page. PCBKit places them on a board for you when you design with it.
What package is the PCAL6408ABSHP?
HVQFN-16-EP(3x3), with 17 pins. Its footprint is drawn on this page.
Where is the PCAL6408ABSHP datasheet?
NXP Semiconductors publishes it: the Datasheet link on this page opens it.
Where can I order the PCAL6408ABSHP?
JLCPCB lists it as part C2652332, with 68 in stock; the sellers' links on this page open their listings.
What can replace the PCAL6408ABSHP?
Parts like it in the library: the PCA9539DBR by Texas Instruments, the PCA9538ABSHP by NXP Semiconductors, the PCF8575DGVR by Texas Instruments and the TPT29548A-QF8R by 3PEAK. Check their datasheets: a part that fits the footprint may still differ in its ratings.
Which open-source boards use the PCAL6408ABSHP?
1 board in 1 repository on GitHub; the most starred are listed on this page, with their KiCad files.