NTS0102DP

Q: Is there a KiCad symbol and footprint for the NTS0102DP?

Yes. The symbol is NTS0102_TSSOP:NTS0102_TSSOP and the footprint Package_SO:TSSOP-8_4.4x3mm_P0.65mm, both drawn on this page. PCBKit places them on a board for you when you design with it.

Q: What package is the NTS0102DP?

TSSOP-8, with 8 pins. Its footprint is drawn on this page.

Q: Where is the NTS0102DP datasheet?

NXP Semiconductors publishes it: the Datasheet link on this page opens it.

Q: Where can I order the NTS0102DP?

JLCPCB lists it as part C2802636, with 2,869 in stock; the sellers' links on this page open their listings.

Q: What can replace the NTS0102DP?

Parts like it in the library: the PCA9306DP1 by NXP Semiconductors, the NCA9306-DTSHR by NOVOSENSE, the AIPTB0102TA8.TR by Wuxi I-core Elec and the NVT2002DP by NXP Semiconductors. Check their datasheets: a part that fits the footprint may still differ in its ratings.

Q: Which open-source boards use the NTS0102DP?

3 boards in 3 repositories on GitHub; the most starred are listed on this page, with their KiCad files.

NXP Semiconductors

-40℃~+125℃ 1.65V~3.6V 2 2.3V~5.5V 50Mbps Auto Direction Detection、Power-Off Protection Bidirectional Tri-State TSSOP-8 Translators, Level Shifters ROHS

Extended

Datasheetnxp/NTS0102DP

Category: Translators, Level Shifters
Package: TSSOP-8
Pins: 8

Overview

The NTS0102DP is a translators, Level Shifter made by NXP Semiconductors in a TSSOP-8 package with 8 pins. -40℃~+125℃ 1.65V~3.6V 2 2.3V~5.5V 50Mbps Auto Direction Detection、Power-Off Protection Bidirectional Tri-State TSSOP-8 Translators, Level Shifters ROHS.

PCBKit's library has its KiCad symbol (NTS0102_TSSOP:NTS0102_TSSOP, from Antmicro) and its footprint (Package_SO:TSSOP-8_4.4x3mm_P0.65mm, from KiCad's library), ready for a KiCad board. 2,869 are in stock at JLCPCB (part C2802636). 3 open-source boards in 3 repositories on GitHub use it.

Symbol

NTS0102_TSSOP:NTS0102_TSSOPFrom Antmicro

Footprint

Package_SO:TSSOP-8_4.4x3mm_P0.65mmFrom KiCad's library

From the datasheet

Supply, least: 1.65 V · VCC(A), recommended operating min · p. 5
Supply, most: 3.6 V · VCC(A), recommended operating max · p. 5
Supply, least: 2.3 V · VCC(B), recommended operating min · p. 5
Supply, most: 5.5 V · VCC(B), recommended operating max · p. 5
Supply, absolute maximum: 6.5 V · VCC(A), absolute max · p. 5
Works from: -40 °C · ambient temperature min · p. 5
Works up to: 125 °C · ambient temperature max · p. 5
Takes working: 4.7 µA · sum of ICC(A) and ICC(B), typical at VCC(A) = 1.8 V, VCC(B) = 5.0 V, 25 °C · p. 6
Takes at most: 30 µA · sum of ICC(A) and ICC(B), max over -40 °C to +125 °C; VI = 0 V or VCCI, IO = 0 A · p. 8
A pin gives at most: 50 mA · output current absolute max, VO = 0 V to VCCO · p. 5
Data rate, most: 50 Mbit/s · push-pull data rate max · p. 1

What it is and has

Function: Dual supply translating transceiver; open-drain; auto direction sensing · p. 1
Data width: 2-bit, bidirectional voltage level translation · p. 1
Supply voltage range: VCC(A): 1.65 V to 3.6 V; VCC(B): 2.3 V to 5.5 V · p. 1
Maximum data rate: Push-pull: 50 Mbit/s · p. 1
Partial power-down: IOFF circuitry · p. 1
Input voltage tolerance: Up to 5.5 V · p. 1
ESD protection, A port: HBM JESD22-A114E Class 2 exceeds 2500 V · p. 1
ESD protection, B port: HBM JESD22-A114E Class 3B exceeds 8000 V · p. 1
ESD protection, CDM: JESD22-C101E exceeds 1500 V · p. 1
Latch-up performance: Exceeds 100 mA per JESD 78B Class II · p. 1
Package: TSSOP8, SOT505-2 · p. 1

Specifications

138

Parameter	Conditions	As printed	Page
supply voltage A VCC(A)		min -0.5 · max 6.5 V	5
supply voltage B VCC(B)		min -0.5 · max 6.5 V	5
input voltage VI	A port and OE input	min -0.5 · max 6.5 V	5
input voltage VI	B port	min -0.5 · max 6.5 V	5
output voltage VO	Active mode; A or B port	min -0.5 V	5
output voltage VO	Power-down or 3-state mode; A port	min -0.5 · max 4.6 V	5
output voltage VO	Power-down or 3-state mode; B port	min -0.5 · max 6.5 V	5
input clamping current IIK	VI < 0 V	min -50 mA	5
output clamping current IOK	VO < 0 V	min -50 mA	5
supply current ICC	ICC(A) or ICC(B)	max 100 mA	5
ground current IGND		min -100 mA	5
storage temperature Tstg		min -65 · max 150 °C	5
total power dissipation Ptot	Tamb = -40 °C to +125 °C; TSSOP8: above 55 °C derates linearly with 2.5 mW/K	max 250 mW	5
supply voltage A VCC(A)		min 1.65 · max 3.6 V	5
supply voltage B VCC(B)		min 2.3 · max 5.5 V	5
ambient temperature Tamb		min -40 · max 125 °C	5
input transition rise and fall rate Δt/ΔV	A or B port; push-pull driving; VCC(A) = 1.65 V to 3.6 V; VCC(B) = 2.3 V to 5.5 V	max 10 ns/V	5
input transition rise and fall rate Δt/ΔV	OE input; VCC(A) = 1.65 V to 3.6 V; VCC(B) = 2.3 V to 5.5 V	max 10 ns/V	5
input capacitance CI	Tamb = 25 °C; OE input; VCC(A) = 3.3 V; VCC(B) = 3.3 V	typ 1 pF	6
input/output capacitance CI/O	Tamb = 25 °C; A port	typ 5 pF	6
input/output capacitance CI/O	Tamb = 25 °C; B port	typ 8.5 pF	6
input/output capacitance CI/O	Tamb = 25 °C; A or B port; VCC(A) = 3.3 V; VCC(B) = 3.3 V	typ 11 pF	6
supply current ICC(A)	Tamb = 25 °C; VCC(A) = 1.8 V; VCC(B) = 2.5 V	typ 0.1 uA	6
supply current ICC(A)	Tamb = 25 °C; VCC(A) = 1.8 V; VCC(B) = 3.3 V	typ 0.1 uA	6
supply current ICC(A)	Tamb = 25 °C; VCC(A) = 1.8 V; VCC(B) = 5.0 V	typ 0.1 uA	6
supply current ICC(A)	Tamb = 25 °C; VCC(A) = 2.5 V; VCC(B) = 2.5 V	typ 0.1 uA	6
supply current ICC(A)	Tamb = 25 °C; VCC(A) = 2.5 V; VCC(B) = 3.3 V	typ 0.1 uA	6
supply current ICC(A)	Tamb = 25 °C; VCC(A) = 2.5 V; VCC(B) = 5.0 V	typ 0.1 uA	6
supply current ICC(A)	Tamb = 25 °C; VCC(A) = 3.3 V; VCC(B) = 3.3 V	typ 0.1 uA	6
supply current ICC(A)	Tamb = 25 °C; VCC(A) = 3.3 V; VCC(B) = 5.0 V	typ 0.1 uA	6
LOW-level input voltage VIL	-40 °C to +85 °C; A or B port; VCC(A) = 1.65 V to 3.6 V; VCC(B) = 2.3 V to 5.5 V	max 0.15 V	7
LOW-level input voltage VIL	-40 °C to +125 °C; A or B port; VCC(A) = 1.65 V to 3.6 V; VCC(B) = 2.3 V to 5.5 V	max 0.15 V	7
LOW-level output voltage VOL	-40 °C to +85 °C; A or B port; IO = 1 mA; VI ≤ 0.15 V; VCC(A) = 1.65 V to 3.6 V; VCC(B) = 2.3 V to 5.5 V	max 0.4 V	7
LOW-level output voltage VOL	-40 °C to +125 °C; A or B port; IO = 1 mA; VI ≤ 0.15 V; VCC(A) = 1.65 V to 3.6 V; VCC(B) = 2.3 V to 5.5 V	max 0.4 V	7
supply current ICC	-40 °C to +85 °C; ICC(A); VI = 0 V or VCCI; IO = 0 A; VCC(A) = 1.65 V to 3.6 V; VCC(B) = 2.3 V to 5.5 V	max 2.4 uA	7
supply current ICC	-40 °C to +125 °C; ICC(A); VI = 0 V or VCCI; IO = 0 A; VCC(A) = 1.65 V to 3.6 V; VCC(B) = 2.3 V to 5.5 V	max 15 uA	7
supply current ICC	-40 °C to +85 °C; ICC(A); VI = 0 V or VCCI; IO = 0 A; VCC(A) = 3.6 V; VCC(B) = 0 V	max 2.2 uA	7
supply current ICC	-40 °C to +125 °C; ICC(A); VI = 0 V or VCCI; IO = 0 A; VCC(A) = 3.6 V; VCC(B) = 0 V	max 15 uA	7
supply current ICC	-40 °C to +85 °C; ICC(A); VI = 0 V or VCCI; IO = 0 A; VCC(A) = 0 V; VCC(B) = 5.5 V	max -1 uA	7
supply current ICC	-40 °C to +125 °C; ICC(A); VI = 0 V or VCCI; IO = 0 A; VCC(A) = 0 V; VCC(B) = 5.5 V	max -8 uA	7
supply current ICC	-40 °C to +85 °C; ICC(B); VI = 0 V or VCCI; IO = 0 A; VCC(A) = 1.65 V to 3.6 V; VCC(B) = 2.3 V to 5.5 V	max 12 uA	7
supply current ICC	-40 °C to +125 °C; ICC(B); VI = 0 V or VCCI; IO = 0 A; VCC(A) = 1.65 V to 3.6 V; VCC(B) = 2.3 V to 5.5 V	max 30 uA	7
supply current ICC	-40 °C to +85 °C; ICC(B); VI = 0 V or VCCI; IO = 0 A; VCC(A) = 3.6 V; VCC(B) = 0 V	max -1 uA	7
supply current ICC	-40 °C to +125 °C; ICC(B); VI = 0 V or VCCI; IO = 0 A; VCC(A) = 3.6 V; VCC(B) = 0 V	max -5 uA	7
supply current ICC	-40 °C to +85 °C; ICC(B); VI = 0 V or VCCI; IO = 0 A; VCC(A) = 0 V; VCC(B) = 5.5 V	max 1 uA	7
supply current ICC	-40 °C to +125 °C; ICC(B); VI = 0 V or VCCI; IO = 0 A; VCC(A) = 0 V; VCC(B) = 5.5 V	max 6 uA	7
supply current ICC	-40 °C to +85 °C; ICC(A) + ICC(B); VI = 0 V or VCCI; IO = 0 A; VCC(A) = 1.65 V to 3.6 V; VCC(B) = 2.3 V to 5.5 V	max 14.4 uA	8
supply current ICC	-40 °C to +125 °C; ICC(A) + ICC(B); VI = 0 V or VCCI; IO = 0 A; VCC(A) = 1.65 V to 3.6 V; VCC(B) = 2.3 V to 5.5 V	max 30 uA	8
HIGH to LOW propagation delay tPHL	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 2.5 V ± 0.2 V; A to B	max 4.6 ns	8
HIGH to LOW propagation delay tPHL	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 3.3 V ± 0.3 V; A to B	max 4.7 ns	8
HIGH to LOW propagation delay tPHL	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 5.0 V ± 0.5 V; A to B	max 5.8 ns	8
LOW to HIGH propagation delay tPLH	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 2.5 V ± 0.2 V; A to B	max 6.8 ns	8
LOW to HIGH propagation delay tPLH	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 3.3 V ± 0.3 V; A to B	max 6.8 ns	8
LOW to HIGH propagation delay tPLH	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 5.0 V ± 0.5 V; A to B	max 7 ns	8
HIGH to LOW propagation delay tPHL	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 2.5 V ± 0.2 V; B to A	max 4.4 ns	8
HIGH to LOW propagation delay tPHL	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 3.3 V ± 0.3 V; B to A	max 4.5 ns	8
HIGH to LOW propagation delay tPHL	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 5.0 V ± 0.5 V; B to A	max 4.7 ns	8
LOW to HIGH propagation delay tPLH	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 2.5 V ± 0.2 V; B to A	max 5.3 ns	8
LOW to HIGH propagation delay tPLH	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 3.3 V ± 0.3 V; B to A	max 4.5 ns	8
LOW to HIGH propagation delay tPLH	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 5.0 V ± 0.5 V; B to A	max 0.5 ns	8
enable time ten	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 2.5 V ± 0.2 V; OE to A; B	max 200 ns	8
enable time ten	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 3.3 V ± 0.3 V; OE to A; B	max 200 ns	8
enable time ten	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 5.0 V ± 0.5 V; OE to A; B	max 200 ns	8
disable time tdis	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 2.5 V ± 0.2 V; OE to A; no external load	max 25 ns	8
disable time tdis	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 3.3 V ± 0.3 V; OE to A; no external load	max 25 ns	8
disable time tdis	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 5.0 V ± 0.5 V; OE to A; no external load	max 25 ns	8
disable time tdis	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 2.5 V ± 0.2 V; OE to B; no external load	max 25 ns	8
disable time tdis	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 3.3 V ± 0.3 V; OE to B; no external load	max 25 ns	8
disable time tdis	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 5.0 V ± 0.5 V; OE to B; no external load	max 25 ns	8
disable time tdis	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 2.5 V ± 0.2 V; OE to A	max 230 ns	8
disable time tdis	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 3.3 V ± 0.3 V; OE to A	max 230 ns	8
disable time tdis	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 5.0 V ± 0.5 V; OE to A	max 230 ns	8
disable time tdis	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 2.5 V ± 0.2 V; OE to B	max 200 ns	8
disable time tdis	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 3.3 V ± 0.3 V; OE to B	max 200 ns	8
disable time tdis	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 5.0 V ± 0.5 V; OE to B	max 200 ns	8
LOW to HIGH output transition time tTLH	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 2.5 V ± 0.2 V; A port	min 3.2 · max 9.5 ns	8
LOW to HIGH output transition time tTLH	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 3.3 V ± 0.3 V; A port	min 2.3 · max 9.3 ns	8
LOW to HIGH output transition time tTLH	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 5.0 V ± 0.5 V; A port	min 1.8 · max 7.6 ns	8
LOW to HIGH output transition time tTLH	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 2.5 V ± 0.2 V; B port	min 3.3 · max 10.8 ns	8
LOW to HIGH output transition time tTLH	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 3.3 V ± 0.3 V; B port	min 2.7 · max 9.1 ns	8
LOW to HIGH output transition time tTLH	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 5.0 V ± 0.5 V; B port	min 2.7 · max 7.6 ns	8
HIGH to LOW output transition time tTHL	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 2.5 V ± 0.2 V; A port	min 2 · max 5.9 ns	8
HIGH to LOW output transition time tTHL	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 3.3 V ± 0.3 V; A port	min 1.9 · max 6 ns	8
HIGH to LOW output transition time tTHL	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 5.0 V ± 0.5 V; A port	min 1.7 · max 13.3 ns	8
HIGH to LOW output transition time tTHL	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 2.5 V ± 0.2 V; B port	min 2.9 · max 7.6 ns	8
HIGH to LOW output transition time tTHL	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 3.3 V ± 0.3 V; B port	min 2.8 · max 7.5 ns	8
HIGH to LOW output transition time tTHL	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 5.0 V ± 0.5 V; B port	min 2.8 · max 10 ns	8
output skew time tsk(o)	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 2.5 V ± 0.2 V; between channels	max 0.7 ns	8
output skew time tsk(o)	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 3.3 V ± 0.3 V; between channels	max 0.7 ns	8
output skew time tsk(o)	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 5.0 V ± 0.5 V; between channels	max 0.7 ns	8
pulse width tW	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 2.5 V ± 0.2 V; data inputs	min 20 ns	8
pulse width tW	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 3.3 V ± 0.3 V; data inputs	min 20 ns	8
pulse width tW	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 5.0 V ± 0.5 V; data inputs	min 20 ns	8
data rate fdata	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 2.5 V ± 0.2 V	max 50 Mbit/s	8
data rate fdata	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 3.3 V ± 0.3 V	max 50 Mbit/s	8
data rate fdata	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 5.0 V ± 0.5 V	max 50 Mbit/s	8
HIGH to LOW propagation delay tPHL	VCC(A) = 2.5 V ± 0.2 V; VCC(B) = 2.5 V ± 0.2 V; A to B	max 3.2 ns	8
HIGH to LOW propagation delay tPHL	VCC(A) = 2.5 V ± 0.2 V; VCC(B) = 3.3 V ± 0.3 V; A to B	max 3.3 ns	8
HIGH to LOW propagation delay tPHL	VCC(A) = 2.5 V ± 0.2 V; VCC(B) = 5.0 V ± 0.5 V; A to B	max 3.4 ns	8
HIGH to LOW propagation delay tPHL	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 2.5 V ± 0.2 V; A to B	max 5.8 ns	10
HIGH to LOW propagation delay tPHL	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 3.3 V ± 0.3 V; A to B	max 5.9 ns	10
HIGH to LOW propagation delay tPHL	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 5.0 V ± 0.5 V; A to B	max 7.3 ns	10
LOW to HIGH propagation delay tPLH	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 2.5 V ± 0.2 V; A to B	max 8.5 ns	10
LOW to HIGH propagation delay tPLH	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 3.3 V ± 0.3 V; A to B	max 8.5 ns	10
LOW to HIGH propagation delay tPLH	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 5.0 V ± 0.5 V; A to B	max 8.8 ns	10
HIGH to LOW propagation delay tPHL	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 2.5 V ± 0.2 V; B to A	max 5.5 ns	10
HIGH to LOW propagation delay tPHL	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 3.3 V ± 0.3 V; B to A	max 5.7 ns	10
HIGH to LOW propagation delay tPHL	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 5.0 V ± 0.5 V; B to A	max 5.9 ns	10
LOW to HIGH propagation delay tPLH	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 2.5 V ± 0.2 V; B to A	max 6.7 ns	10
LOW to HIGH propagation delay tPLH	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 3.3 V ± 0.3 V; B to A	max 5.7 ns	10
LOW to HIGH propagation delay tPLH	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 5.0 V ± 0.5 V; B to A	max 0.7 ns	10
disable time tdis	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 2.5 V ± 0.2 V; OE to A; no external load	max 30 ns	10
disable time tdis	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 3.3 V ± 0.3 V; OE to A; no external load	max 30 ns	10
disable time tdis	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 5.0 V ± 0.5 V; OE to A; no external load	max 30 ns	10
disable time tdis	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 2.5 V ± 0.2 V; OE to B; no external load	max 30 ns	10
disable time tdis	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 3.3 V ± 0.3 V; OE to B; no external load	max 30 ns	10
disable time tdis	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 5.0 V ± 0.5 V; OE to B; no external load	max 30 ns	10
disable time tdis	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 2.5 V ± 0.2 V; OE to A	max 250 ns	10
disable time tdis	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 3.3 V ± 0.3 V; OE to A	max 250 ns	10
disable time tdis	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 5.0 V ± 0.5 V; OE to A	max 250 ns	10
disable time tdis	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 2.5 V ± 0.2 V; OE to B	max 220 ns	10
disable time tdis	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 3.3 V ± 0.3 V; OE to B	max 220 ns	10
disable time tdis	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 5.0 V ± 0.5 V; OE to B	max 220 ns	10
LOW to HIGH output transition time tTLH	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 2.5 V ± 0.2 V; A port	min 3.2 · max 11.9 ns	10
LOW to HIGH output transition time tTLH	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 3.3 V ± 0.3 V; A port	min 2.3 · max 11.7 ns	10
LOW to HIGH output transition time tTLH	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 5.0 V ± 0.5 V; A port	min 1.8 · max 9.5 ns	10
LOW to HIGH output transition time tTLH	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 2.5 V ± 0.2 V; B port	min 3.3 · max 13.5 ns	10
LOW to HIGH output transition time tTLH	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 3.3 V ± 0.3 V; B port	min 2.7 · max 11.4 ns	10
LOW to HIGH output transition time tTLH	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 5.0 V ± 0.5 V; B port	min 2.7 · max 9.5 ns	10
HIGH to LOW output transition time tTHL	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 2.5 V ± 0.2 V; A port	min 2 · max 7.4 ns	10
HIGH to LOW output transition time tTHL	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 3.3 V ± 0.3 V; A port	min 1.9 · max 7.5 ns	10
HIGH to LOW output transition time tTHL	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 5.0 V ± 0.5 V; A port	min 1.7 · max 16.7 ns	10
HIGH to LOW output transition time tTHL	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 2.5 V ± 0.2 V; B port	min 2.9 · max 9.5 ns	10
HIGH to LOW output transition time tTHL	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 3.3 V ± 0.3 V; B port	min 2.8 · max 9.4 ns	10
HIGH to LOW output transition time tTHL	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 5.0 V ± 0.5 V; B port	min 2.8 · max 12.5 ns	10
output skew time tsk(o)	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 2.5 V ± 0.2 V; between channels	max 0.8 ns	10
output skew time tsk(o)	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 3.3 V ± 0.3 V; between channels	max 0.8 ns	10
output skew time tsk(o)	VCC(A) = 1.8 V ± 0.15 V; VCC(B) = 5.0 V ± 0.5 V; between channels	max 0.8 ns	10

Pins, by the datasheet

1 B2: Data input or output referenced to VCC(B). · p. 4
2 GND: Ground (0 V). · p. 4
3 VCC(A): Supply voltage A. · p. 4
4 A2: Data input or output referenced to VCC(A). · p. 4
5 A1: Data input or output referenced to VCC(A). · p. 4
6 OE: Output enable input, active HIGH, referenced to VCC(A). · p. 4
7 VCC(B): Supply voltage B. · p. 4
8 B1: Data input or output referenced to VCC(B). · p. 4

Ordering codes, by the datasheet

NTS0102DP,125: TSSOP8 · Reel 7" Q3 NDP; minimum order quantity 3000; –40 °C to +125 °C · p. 2

Parameters

Channel Type: Bidirectional
Current - Supply: 4.7uA
Current - Supply(Max): 30uA
Data Rate: 50Mbps
Features: Automatic direction detection
Interface: SMBus
Number of Circuits: 2
Operating Temperature: -40℃~+125℃
Output Current per Pin(Max): 50mA
Output Type: Tri-State
Translator Type: Level translator
Voltage - Supply: 1.65V~5.5V
Voltage - Supply(Absolute Max): 6.5V
Voltage - Supply(VCCA): 1.65V~3.6V
Voltage - Supply(VCCB): 2.3V~5.5V

Order codes

NTS0102DP,125LCSC C2802636

Pinout

The pins of the NTS0102DP
Pin	Name	Type
1	B_{2}	Input/output
2	GND	Power in
3	VCC_{A}	Power in
4	A_{2}	Input/output
5	A_{1}	Input/output
6	OE	Input
7	VCC_{B}	Power in
8	B_{1}	Input/output

Open-source boards using it

All 3

8 layers227.5 × 104 mm
Com express-7-baseboard
antmicro/com-express-7-baseboard
This project contains open hardware design files for a baseboard supporting COM Express 7 modules. The board breaks-out major communications and peripheral interfaces provided by the standard.
815 parts12Apache-2.0
4 layers100 × 100 mm
Cm5-module
Dominik-Workshop/moducard-cm5-module
ModuCard module for CM5
306 parts5MIT
4 layers75 × 60 mm
Gmsl deserializer
Jsnchg/Driver-UI-vehicle-system-ADAS

237 parts

Show this part on your page

A live frame, for any web page

<iframe src="https://pcbkit.io/embed/parts/nxp/NTS0102DP" title="NTS0102DP in PCBKit" width="100%" height="480" style="border:0;border-radius:12px" allow="fullscreen" loading="lazy"></iframe>

A picture

<img src="https://pcbkit.io/embed/parts/nxp/NTS0102DP.jpg" alt="NTS0102DP" width="1200" height="900">

A picture that opens the part, for a README

[![NTS0102DP](https://pcbkit.io/embed/parts/nxp/NTS0102DP.jpg?size=s)](https://pcbkit.io/parts/nxp/NTS0102DP)

Questions

Is there a KiCad symbol and footprint for the NTS0102DP?

Yes. The symbol is NTS0102_TSSOP:NTS0102_TSSOP and the footprint Package_SO:TSSOP-8_4.4x3mm_P0.65mm, both drawn on this page. PCBKit places them on a board for you when you design with it.

What package is the NTS0102DP?

TSSOP-8, with 8 pins. Its footprint is drawn on this page.

Where is the NTS0102DP datasheet?

NXP Semiconductors publishes it: the Datasheet link on this page opens it.

Where can I order the NTS0102DP?

JLCPCB lists it as part C2802636, with 2,869 in stock; the sellers' links on this page open their listings.

What can replace the NTS0102DP?

Parts like it in the library: the PCA9306DP1 by NXP Semiconductors, the NCA9306-DTSHR by NOVOSENSE, the AIPTB0102TA8.TR by Wuxi I-core Elec and the NVT2002DP by NXP Semiconductors. Check their datasheets: a part that fits the footprint may still differ in its ratings.

Which open-source boards use the NTS0102DP?

3 boards in 3 repositories on GitHub; the most starred are listed on this page, with their KiCad files.

NTS0102DP

Overview

Symbol

Footprint

From the datasheet

What it is and has

Specifications

Pins, by the datasheet

Ordering codes, by the datasheet

Parameters

Order codes

Pinout

Open-source boards using it

Com express-7-baseboard

Cm5-module

Gmsl deserializer

Show this part on your page

Questions

Is there a KiCad symbol and footprint for the NTS0102DP?

What package is the NTS0102DP?

Where is the NTS0102DP datasheet?

Where can I order the NTS0102DP?

What can replace the NTS0102DP?

Which open-source boards use the NTS0102DP?

Parts like it

PCA9306DP1

NCA9306-DTSHR

AIPTB0102TA8.TR

NVT2002DP

NB100ELT23LDT

MC100EPT20DT

MC100EPT23DT

PCA9306DP