4 layers60 × 28 mm
74LVC2T45DC
NexperiaExtended
-40℃~+125℃ 1 1.2V~5.5V 1.2V~5.5V 2 420Mbps Bidirectional Power-Off Protection Tri-State VSSOP-8-0.5mm Translators, Level Shifters ROHS
- Part id
- nexperia/74LVC2T45DC
- Category
- Translators, Level Shifters
- Package
- VSSOP-8-0.5mm
- Pins
- 8
- In stock
- 55,172 at JLCPCB (C730237)
- Used on
- 47 open-source boards
Overview
The 74LVC2T45DC is a translators, Level Shifter made by Nexperia in a VSSOP-8-0.5mm package with 8 pins. -40℃~+125℃ 1 1.2V~5.5V 1.2V~5.5V 2 420Mbps Bidirectional Power-Off Protection Tri-State VSSOP-8-0.5mm Translators, Level Shifters ROHS.
PCBKit's library has its KiCad symbol (Logic_LevelTranslator:74LVC2T45DC, from KiCad's library) and its footprint (Package_SO:VSSOP-8_3x3mm_P0.65mm, from KiCad's library), ready for a KiCad board. 55,172 are in stock at JLCPCB (part C730237). 47 open-source boards in 40 repositories on GitHub use it.
Symbol
Footprint
From the datasheet
8- Supply, least
- 1.2 V · VCC(A), recommended operating min · p. 5
- Supply, most
- 5.5 V · VCC(A), recommended operating max · p. 5
- Supply, absolute maximum
- 6.5 V · VCC(A), absolute max · p. 4
- Works from
- -40 °C · ambient temperature min · p. 5
- Works up to
- 125 °C · ambient temperature max · p. 5
- A pin gives at most
- 50 mA · output source or sink current absolute max; VO = 0 V to VCCO · p. 4
- Takes working
- 16 µA · sum of A and B supply currents max; supplies 1.2 V to 5.5 V; IO = 0 A; VI = 0 V or VCCI · p. 8
- Data rate, most
- 420 Mbit/s · max; 3.3 V to 5.0 V translation · p. 1
What it is and has
12- Function
- Dual supply translating transceiver; 3-state · p. 1
- Maximum data rate
- 420 Mbps, 3.3 V to 5.0 V translation · p. 1
- Maximum data rate
- 210 Mbps, translation to 3.3 V · p. 1
- Maximum data rate
- 140 Mbps, translation to 2.5 V · p. 1
- Maximum data rate
- 75 Mbps, translation to 1.8 V · p. 1
- Maximum data rate
- 60 Mbps, translation to 1.5 V · p. 1
- Output drive
- ±24 mA at VCC = 3.0 V · p. 1
- Partial power-down
- IOFF circuitry · p. 1
- ESD protection
- HBM class 3A, exceeds 4000 V · p. 1
- ESD protection
- CDM class C3, exceeds 1000 V · p. 1
- Latch-up performance
- Exceeds 100 mA per JESD 78 Class II · p. 1
- Noise immunity
- High · p. 1
Specifications
194| Parameter | Conditions | As printed | Page |
|---|---|---|---|
| supply voltage A VCC(A) | min -0.5 · max 6.5 V | 4 | |
| supply voltage B VCC(B) | min -0.5 · max 6.5 V | 4 | |
| input clamping current IIK | VI < 0 V | min -50 mA | 4 |
| input voltage VI | [1] | min -0.5 · max 6.5 V | 4 |
| output clamping current IOK | VO < 0 V | min -50 mA | 4 |
| output voltage VO | Active mode; [1][2][3]; maximum VCCO + 0.5 V | min -0.5 V | 4 |
| output voltage VO | Suspend or 3-state mode; [1] | min -0.5 · max 6.5 V | 4 |
| output current IO | VO = 0 V to VCCO; [2]; ±50 mA | max 50 mA | 4 |
| supply current ICC | ICC(A) or ICC(B) | max 100 mA | 4 |
| ground current IGND | min -100 mA | 4 | |
| storage temperature Tstg | min -65 · max 150 °C | 4 | |
| total power dissipation Ptot | Tamb = -40 °C to +125 °C; SOT765-1 (VSSOP8); derates 4.9 mW/K above 99 °C | max 250 mW | 4 |
| supply voltage A VCC(A) | min 1.2 · max 5.5 V | 5 | |
| supply voltage B VCC(B) | min 1.2 · max 5.5 V | 5 | |
| input voltage VI | min 0 · max 5.5 V | 5 | |
| output voltage VO | Active mode; maximum VCCO, the supply associated with the output port | min 0 V | 5 |
| output voltage VO | Suspend or 3-state mode | min 0 · max 5.5 V | 5 |
| ambient temperature Tamb | min -40 · max 125 °C | 5 | |
| input transition rise and fall rate Δt/ΔV | VCCI = 1.2 V | max 20 ns/V | 5 |
| input transition rise and fall rate Δt/ΔV | VCCI = 1.4 V to 1.95 V | max 20 ns/V | 5 |
| input transition rise and fall rate Δt/ΔV | VCCI = 2.3 V to 2.7 V | max 20 ns/V | 5 |
| input transition rise and fall rate Δt/ΔV | VCCI = 3 V to 3.6 V | max 10 ns/V | 5 |
| input transition rise and fall rate Δt/ΔV | VCCI = 4.5 V to 5.5 V | max 5 ns/V | 5 |
| HIGH-level output voltage VOH | VI = VIH or VIL; IO = -3 mA; VCCO = 1.2 V | typ 1.09 V | 5 |
| LOW-level output voltage VOL | VI = VIH or VIL; IO = 3 mA; VCCO = 1.2 V | typ 0.07 V | 5 |
| input leakage current II | DIR input; VI = 0 V to 5.5 V; VCCI = 1.2 V to 5.5 V; ±1 uA | max 1 uA | 5 |
| OFF-state output current IOZ | A or B port; VO = 0 V or VCCO; VCCO = 1.2 V to 5.5 V; ±1 uA | max 1 uA | 5 |
| power-off leakage current IOFF | A port; VI or VO = 0 V to 5.5 V; VCC(A) = 0 V; VCC(B) = 1.2 V to 5.5 V; ±1 uA | max 1 uA | 5 |
| power-off leakage current IOFF | B port; VI or VO = 0 V to 5.5 V; VCC(B) = 0 V; VCC(A) = 1.2 V to 5.5 V; ±1 uA | max 1 uA | 5 |
| input capacitance CI | DIR input; VI = 0 V or 3.3 V; VCC(A) = VCC(B) = 3.3 V | typ 2.2 pF | 5 |
| input/output capacitance CI/O | A and B port; suspend mode; VO = 3.3 V or 0 V; VCC(A) = VCC(B) = 3.3 V | typ 6 pF | 5 |
| HIGH-level input voltage VIH | data input; VCCI = 2.3 V to 2.7 V; -40 °C to +85 °C and -40 °C to +125 °C | min 1.7 V | 6 |
| HIGH-level input voltage VIH | data input; VCCI = 3.0 V to 3.6 V; -40 °C to +85 °C and -40 °C to +125 °C | min 2 V | 6 |
| HIGH-level input voltage VIH | DIR input; VCCI = 2.3 V to 2.7 V; -40 °C to +85 °C and -40 °C to +125 °C | min 1.7 V | 6 |
| HIGH-level input voltage VIH | DIR input; VCCI = 3.0 V to 3.6 V; -40 °C to +85 °C and -40 °C to +125 °C | min 2 V | 6 |
| LOW-level input voltage VIL | data input; VCCI = 2.3 V to 2.7 V; -40 °C to +85 °C and -40 °C to +125 °C | max 0.7 V | 6 |
| LOW-level input voltage VIL | data input; VCCI = 3.0 V to 3.6 V; -40 °C to +85 °C and -40 °C to +125 °C | max 0.8 V | 6 |
| LOW-level input voltage VIL | DIR input; VCCI = 2.3 V to 2.7 V; -40 °C to +85 °C and -40 °C to +125 °C | max 0.7 V | 6 |
| LOW-level input voltage VIL | DIR input; VCCI = 3.0 V to 3.6 V; -40 °C to +85 °C and -40 °C to +125 °C | max 0.8 V | 6 |
| HIGH-level output voltage VOH | VI = VIH; IO = -6 mA; VCCO = 1.4 V; -40 °C to +85 °C and -40 °C to +125 °C | min 1 V | 6 |
| HIGH-level output voltage VOH | VI = VIH; IO = -8 mA; VCCO = 1.65 V; -40 °C to +85 °C and -40 °C to +125 °C | min 1.2 V | 6 |
| HIGH-level output voltage VOH | VI = VIH; IO = -12 mA; VCCO = 2.3 V; -40 °C to +85 °C and -40 °C to +125 °C | min 1.9 V | 6 |
| HIGH-level output voltage VOH | VI = VIH; IO = -24 mA; VCCO = 3.0 V; -40 °C to +85 °C and -40 °C to +125 °C | min 2.4 V | 6 |
| HIGH-level output voltage VOH | VI = VIH; IO = -32 mA; VCCO = 4.5 V; -40 °C to +85 °C and -40 °C to +125 °C | min 3.8 V | 6 |
| LOW-level output voltage VOL | VI = VIL; IO = 100 uA; VCCO = 1.2 V to 4.5 V; -40 °C to +85 °C and -40 °C to +125 °C | max 0.1 V | 6 |
| LOW-level output voltage VOL | VI = VIL; IO = 6 mA; VCCO = 1.4 V; -40 °C to +85 °C and -40 °C to +125 °C | max 0.3 V | 6 |
| LOW-level output voltage VOL | VI = VIL; IO = 8 mA; VCCO = 1.65 V; -40 °C to +85 °C and -40 °C to +125 °C | max 0.45 V | 6 |
| LOW-level output voltage VOL | VI = VIL; IO = 12 mA; VCCO = 2.3 V; -40 °C to +85 °C and -40 °C to +125 °C | max 0.3 V | 6 |
| LOW-level output voltage VOL | VI = VIL; IO = 24 mA; VCCO = 3.0 V; -40 °C to +85 °C and -40 °C to +125 °C | max 0.55 V | 6 |
| LOW-level output voltage VOL | VI = VIL; IO = 32 mA; VCCO = 4.5 V; -40 °C to +85 °C and -40 °C to +125 °C | max 0.55 V | 6 |
| input leakage current II | DIR input; VI = 0 V to 5.5 V; VCCI = 1.2 V to 5.5 V; -40 °C to +85 °C; ±2 uA | max 2 uA | 7 |
| input leakage current II | DIR input; VI = 0 V to 5.5 V; VCCI = 1.2 V to 5.5 V; -40 °C to +125 °C; ±10 uA | max 10 uA | 7 |
| OFF-state output current IOZ | A or B port; VO = 0 V or VCCO; VCCO = 1.2 V to 5.5 V; -40 °C to +85 °C; ±2 uA | max 2 uA | 7 |
| OFF-state output current IOZ | A or B port; VO = 0 V or VCCO; VCCO = 1.2 V to 5.5 V; -40 °C to +125 °C; ±10 uA | max 10 uA | 7 |
| power-off leakage current IOFF | A port; VI or VO = 0 V to 5.5 V; VCC(A) = 0 V; VCC(B) = 1.2 V to 5.5 V; -40 °C to +85 °C; ±2 uA | max 2 uA | 7 |
| power-off leakage current IOFF | A port; VI or VO = 0 V to 5.5 V; VCC(A) = 0 V; VCC(B) = 1.2 V to 5.5 V; -40 °C to +125 °C; ±10 uA | max 10 uA | 7 |
| power-off leakage current IOFF | B port; VI or VO = 0 V to 5.5 V; VCC(B) = 0 V; VCC(A) = 1.2 V to 5.5 V; -40 °C to +85 °C; ±2 uA | max 2 uA | 7 |
| power-off leakage current IOFF | B port; VI or VO = 0 V to 5.5 V; VCC(B) = 0 V; VCC(A) = 1.2 V to 5.5 V; -40 °C to +125 °C; ±10 uA | max 10 uA | 7 |
| supply current ICC | A port; VI = 0 V or VCCI; IO = 0 A; VCC(A), VCC(B) = 1.2 V to 5.5 V; -40 °C to +85 °C and -40 °C to +125 °C | max 8 uA | 8 |
| supply current ICC | A port; VI = 0 V or VCCI; IO = 0 A; VCC(A), VCC(B) = 1.65 V to 5.5 V; -40 °C to +85 °C and -40 °C to +125 °C | max 3 uA | 8 |
| supply current ICC | A port; VI = 0 V or VCCI; IO = 0 A; VCC(A) = 5.5 V; VCC(B) = 0 V; -40 °C to +85 °C and -40 °C to +125 °C | max 2 uA | 8 |
| supply current ICC | A port; VI = 0 V or VCCI; IO = 0 A; VCC(A) = 0 V; VCC(B) = 5.5 V; -40 °C to +85 °C and -40 °C to +125 °C | min -2 uA | 8 |
| supply current ICC | B port; VI = 0 V or VCCI; IO = 0 A; VCC(A), VCC(B) = 1.2 V to 5.5 V; -40 °C to +85 °C and -40 °C to +125 °C | max 8 uA | 8 |
| supply current ICC | B port; VI = 0 V or VCCI; IO = 0 A; VCC(A), VCC(B) = 1.65 V to 5.5 V; -40 °C to +85 °C and -40 °C to +125 °C | max 3 uA | 8 |
| supply current ICC | B port; VI = 0 V or VCCI; IO = 0 A; VCC(B) = 0 V; VCC(A) = 5.5 V; -40 °C to +85 °C and -40 °C to +125 °C | min -2 uA | 8 |
| supply current ICC | B port; VI = 0 V or VCCI; IO = 0 A; VCC(B) = 5.5 V; VCC(A) = 0 V; -40 °C to +85 °C and -40 °C to +125 °C | max 2 uA | 8 |
| supply current ICC | A plus B port (ICC(A) + ICC(B)); IO = 0 A; VI = 0 V or VCCI; VCC(A), VCC(B) = 1.2 V to 5.5 V; -40 °C to +85 °C and -40 °C to +125 °C | max 16 uA | 8 |
| supply current ICC | A plus B port (ICC(A) + ICC(B)); IO = 0 A; VI = 0 V or VCCI; VCC(A), VCC(B) = 1.65 V to 5.5 V; -40 °C to +85 °C and -40 °C to +125 °C | max 4 uA | 8 |
| additional supply current ΔICC | 74LVC2T45; per input; VCC(A), VCC(B) = 3.0 V to 5.5 V; A port at VCC(A) - 0.6 V; DIR at VCC(A); B port open; -40 °C to +85 °C | max 50 uA | 8 |
| additional supply current ΔICC | 74LVC2T45; per input; VCC(A), VCC(B) = 3.0 V to 5.5 V; A port at VCC(A) - 0.6 V; DIR at VCC(A); B port open; -40 °C to +125 °C | max 75 uA | 8 |
| additional supply current ΔICC | per input; VCC(A), VCC(B) = 3.0 V to 5.5 V; DIR at VCC(A) - 0.6 V; A port at VCC(A) or GND; B port open; -40 °C to +85 °C | max 50 uA | 8 |
| additional supply current ΔICC | per input; VCC(A), VCC(B) = 3.0 V to 5.5 V; DIR at VCC(A) - 0.6 V; A port at VCC(A) or GND; B port open; -40 °C to +125 °C | max 75 uA | 8 |
| additional supply current ΔICC | 74LVC2T45; per input; VCC(A), VCC(B) = 3.0 V to 5.5 V; B port at VCC(B) - 0.6 V; DIR at GND; A port open; -40 °C to +85 °C | max 50 uA | 8 |
| additional supply current ΔICC | 74LVC2T45; per input; VCC(A), VCC(B) = 3.0 V to 5.5 V; B port at VCC(B) - 0.6 V; DIR at GND; A port open; -40 °C to +125 °C | max 75 uA | 8 |
| LOW to HIGH propagation delay tPLH | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 1.5 V ± 0.1 V; A to B | min 2.2 · max 16.6 ns | 12 |
| LOW to HIGH propagation delay tPLH | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 1.8 V ± 0.15 V; A to B | min 1.9 · max 15.1 ns | 12 |
| LOW to HIGH propagation delay tPLH | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 2.5 V ± 0.2 V; A to B | min 1 · max 7.5 ns | 12 |
| LOW to HIGH propagation delay tPLH | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 3.3 V ± 0.3 V; A to B | min 0.7 · max 5.4 ns | 12 |
| LOW to HIGH propagation delay tPLH | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 5.0 V ± 0.5 V; A to B | min 0.5 · max 3.9 ns | 12 |
| LOW to HIGH propagation delay tPLH | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 1.5 V ± 0.1 V; B to A | min 1.6 · max 10.5 ns | 12 |
| LOW to HIGH propagation delay tPLH | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 1.8 V ± 0.15 V; B to A | min 1.4 · max 6.8 ns | 12 |
| LOW to HIGH propagation delay tPLH | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 2.5 V ± 0.2 V; B to A | min 1 · max 4.8 ns | 12 |
| LOW to HIGH propagation delay tPLH | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 3.3 V ± 0.3 V; B to A | min 0.7 · max 4.4 ns | 12 |
| LOW to HIGH propagation delay tPLH | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 5.0 V ± 0.5 V; B to A | min 0.5 · max 3.9 ns | 12 |
| HIGH to LOW propagation delay tPHL | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 1.5 V ± 0.1 V; A to B | min 2.3 · max 15.3 ns | 12 |
| HIGH to LOW propagation delay tPHL | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 1.8 V ± 0.15 V; A to B | min 1.8 · max 12.2 ns | 12 |
| HIGH to LOW propagation delay tPHL | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 2.5 V ± 0.2 V; A to B | min 1 · max 6.2 ns | 12 |
| HIGH to LOW propagation delay tPHL | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 3.3 V ± 0.3 V; A to B | min 0.7 · max 4.5 ns | 12 |
| HIGH to LOW propagation delay tPHL | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 5.0 V ± 0.5 V; A to B | min 0.5 · max 3.5 ns | 12 |
| HIGH to LOW propagation delay tPHL | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 1.5 V ± 0.1 V; B to A | min 1.7 · max 10.8 ns | 12 |
| HIGH to LOW propagation delay tPHL | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 1.8 V ± 0.15 V; B to A | min 1.7 · max 7 ns | 12 |
| HIGH to LOW propagation delay tPHL | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 2.5 V ± 0.2 V; B to A | min 0.9 · max 4.6 ns | 12 |
| HIGH to LOW propagation delay tPHL | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 3.3 V ± 0.3 V; B to A | min 0.7 · max 4 ns | 12 |
| HIGH to LOW propagation delay tPHL | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 5.0 V ± 0.5 V; B to A | min 0.5 · max 3.5 ns | 12 |
| HIGH to OFF-state propagation delay tPHZ | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 1.5 V ± 0.1 V; DIR to A | min 1.7 · max 5.4 ns | 12 |
| HIGH to OFF-state propagation delay tPHZ | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 1.8 V ± 0.15 V; DIR to A | min 1.7 · max 5.4 ns | 12 |
| HIGH to OFF-state propagation delay tPHZ | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 2.5 V ± 0.2 V; DIR to A | min 1.7 · max 5.4 ns | 12 |
| HIGH to OFF-state propagation delay tPHZ | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 3.3 V ± 0.3 V; DIR to A | min 1.7 · max 5.4 ns | 12 |
| HIGH to OFF-state propagation delay tPHZ | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 5.0 V ± 0.5 V; DIR to A | min 1.7 · max 5.4 ns | 12 |
| HIGH to OFF-state propagation delay tPHZ | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 1.5 V ± 0.1 V; DIR to B | min 2.9 · max 17.3 ns | 12 |
| HIGH to OFF-state propagation delay tPHZ | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 1.8 V ± 0.15 V; DIR to B | min 2.9 · max 16.1 ns | 12 |
| HIGH to OFF-state propagation delay tPHZ | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 2.5 V ± 0.2 V; DIR to B | min 2.3 · max 9.7 ns | 12 |
| HIGH to OFF-state propagation delay tPHZ | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 3.3 V ± 0.3 V; DIR to B | min 2.7 · max 8 ns | 12 |
| HIGH to OFF-state propagation delay tPHZ | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 5.0 V ± 0.5 V; DIR to B | min 2.5 · max 5.7 ns | 12 |
| LOW to OFF-state propagation delay tPLZ | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 1.5 V ± 0.1 V; DIR to A | min 1.4 · max 3.7 ns | 12 |
| LOW to OFF-state propagation delay tPLZ | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 1.8 V ± 0.15 V; DIR to A | min 1.4 · max 3.7 ns | 12 |
| LOW to OFF-state propagation delay tPLZ | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 2.5 V ± 0.2 V; DIR to A | min 1.3 · max 3.7 ns | 12 |
| LOW to OFF-state propagation delay tPLZ | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 3.3 V ± 0.3 V; DIR to A | min 1 · max 3.7 ns | 12 |
| LOW to OFF-state propagation delay tPLZ | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 5.0 V ± 0.5 V; DIR to A | min 0.9 · max 3.7 ns | 12 |
| LOW to OFF-state propagation delay tPLZ | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 1.5 V ± 0.1 V; DIR to B | min 2.3 · max 13.1 ns | 12 |
| LOW to OFF-state propagation delay tPLZ | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 1.8 V ± 0.15 V; DIR to B | min 2.4 · max 12.1 ns | 12 |
| LOW to OFF-state propagation delay tPLZ | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 2.5 V ± 0.2 V; DIR to B | min 1.9 · max 7.4 ns | 12 |
| LOW to OFF-state propagation delay tPLZ | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 3.3 V ± 0.3 V; DIR to B | min 2.3 · max 7 ns | 12 |
| LOW to OFF-state propagation delay tPLZ | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 5.0 V ± 0.5 V; DIR to B | min 1.8 · max 4.5 ns | 12 |
| OFF-state to HIGH propagation delay tPZH | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 1.5 V ± 0.1 V; DIR to A; calculated [1] | max 23.6 ns | 12 |
| OFF-state to HIGH propagation delay tPZH | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 1.8 V ± 0.15 V; DIR to A; calculated [1] | max 18.9 ns | 12 |
| OFF-state to HIGH propagation delay tPZH | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 2.5 V ± 0.2 V; DIR to A; calculated [1] | max 12.2 ns | 12 |
| OFF-state to HIGH propagation delay tPZH | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 3.3 V ± 0.3 V; DIR to A; calculated [1] | max 11.4 ns | 12 |
| OFF-state to HIGH propagation delay tPZH | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 5.0 V ± 0.5 V; DIR to A; calculated [1] | max 8.4 ns | 12 |
| OFF-state to HIGH propagation delay tPZH | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 1.5 V ± 0.1 V; DIR to B; calculated [1] | max 20.3 ns | 12 |
| OFF-state to HIGH propagation delay tPZH | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 1.8 V ± 0.15 V; DIR to B; calculated [1] | max 18.8 ns | 12 |
| OFF-state to HIGH propagation delay tPZH | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 2.5 V ± 0.2 V; DIR to B; calculated [1] | max 11.2 ns | 12 |
| OFF-state to HIGH propagation delay tPZH | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 3.3 V ± 0.3 V; DIR to B; calculated [1] | max 9.1 ns | 12 |
| OFF-state to HIGH propagation delay tPZH | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 5.0 V ± 0.5 V; DIR to B; calculated [1] | max 7.6 ns | 12 |
| OFF-state to LOW propagation delay tPZL | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 1.5 V ± 0.1 V; DIR to A; calculated [1] | max 28.1 ns | 12 |
| OFF-state to LOW propagation delay tPZL | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 1.8 V ± 0.15 V; DIR to A; calculated [1] | max 23.1 ns | 12 |
| OFF-state to LOW propagation delay tPZL | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 2.5 V ± 0.2 V; DIR to A; calculated [1] | max 14.3 ns | 12 |
| OFF-state to LOW propagation delay tPZL | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 3.3 V ± 0.3 V; DIR to A; calculated [1] | max 12 ns | 12 |
| OFF-state to LOW propagation delay tPZL | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 5.0 V ± 0.5 V; DIR to A; calculated [1] | max 9.2 ns | 12 |
| OFF-state to LOW propagation delay tPZL | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 1.5 V ± 0.1 V; DIR to B; calculated [1] | max 20.7 ns | 12 |
| OFF-state to LOW propagation delay tPZL | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 1.8 V ± 0.15 V; DIR to B; calculated [1] | max 17.6 ns | 12 |
| OFF-state to LOW propagation delay tPZL | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 2.5 V ± 0.2 V; DIR to B; calculated [1] | max 11.6 ns | 12 |
| OFF-state to LOW propagation delay tPZL | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 3.3 V ± 0.3 V; DIR to B; calculated [1] | max 9.9 ns | 12 |
| OFF-state to LOW propagation delay tPZL | VCC(A) = 4.5 V to 5.5 V; VCC(B) = 5.0 V ± 0.5 V; DIR to B; calculated [1] | max 8.9 ns | 12 |
| LOW to HIGH propagation delay tPLH | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 1.5 V ± 0.1 V; A to B | min 2.5 · max 23.5 ns | 12 |
| LOW to HIGH propagation delay tPLH | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 1.8 V ± 0.15 V; A to B | min 2.1 · max 19.4 ns | 12 |
| LOW to HIGH propagation delay tPLH | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 2.5 V ± 0.2 V; A to B | min 1.8 · max 14.9 ns | 12 |
| LOW to HIGH propagation delay tPLH | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 3.3 V ± 0.3 V; A to B | min 1.5 · max 13 ns | 12 |
| LOW to HIGH propagation delay tPLH | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 5.0 V ± 0.5 V; A to B | min 1.4 · max 11.6 ns | 12 |
| LOW to HIGH propagation delay tPLH | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 1.5 V ± 0.1 V; B to A | min 2.5 · max 23.5 ns | 12 |
| LOW to HIGH propagation delay tPLH | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 1.8 V ± 0.15 V; B to A | min 2.3 · max 21.1 ns | 12 |
| LOW to HIGH propagation delay tPLH | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 2.5 V ± 0.2 V; B to A | min 2 · max 16.4 ns | 12 |
| LOW to HIGH propagation delay tPLH | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 3.3 V ± 0.3 V; B to A | min 2 · max 13.7 ns | 12 |
| LOW to HIGH propagation delay tPLH | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 5.0 V ± 0.5 V; B to A | min 1.9 · max 13.2 ns | 12 |
| HIGH to LOW propagation delay tPHL | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 1.5 V ± 0.1 V; A to B | min 2.3 · max 21.3 ns | 12 |
| HIGH to LOW propagation delay tPHL | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 1.8 V ± 0.15 V; A to B | min 1.9 · max 16.9 ns | 12 |
| HIGH to LOW propagation delay tPHL | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 2.5 V ± 0.2 V; A to B | min 1.6 · max 13 ns | 12 |
| HIGH to LOW propagation delay tPHL | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 3.3 V ± 0.3 V; A to B | min 1.5 · max 12 ns | 12 |
| HIGH to LOW propagation delay tPHL | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 5.0 V ± 0.5 V; A to B | min 1.5 · max 11.9 ns | 12 |
| HIGH to LOW propagation delay tPHL | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 1.5 V ± 0.1 V; B to A | min 2.3 · max 21.3 ns | 12 |
| HIGH to LOW propagation delay tPHL | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 1.8 V ± 0.15 V; B to A | min 2.1 · max 19.1 ns | 12 |
| HIGH to LOW propagation delay tPHL | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 2.5 V ± 0.2 V; B to A | min 2 · max 14.6 ns | 12 |
| HIGH to LOW propagation delay tPHL | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 3.3 V ± 0.3 V; B to A | min 1.9 · max 12.5 ns | 12 |
| HIGH to LOW propagation delay tPHL | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 5.0 V ± 0.5 V; B to A | min 2 · max 12.1 ns | 12 |
| HIGH to OFF-state propagation delay tPHZ | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 1.5 V ± 0.1 V; DIR to A | min 2.7 · max 20.6 ns | 12 |
| HIGH to OFF-state propagation delay tPHZ | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 1.8 V ± 0.15 V; DIR to A | min 2.7 · max 20.6 ns | 12 |
| HIGH to OFF-state propagation delay tPHZ | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 2.5 V ± 0.2 V; DIR to A | min 2.7 · max 20.6 ns | 12 |
| HIGH to OFF-state propagation delay tPHZ | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 3.3 V ± 0.3 V; DIR to A | min 2.7 · max 20.6 ns | 12 |
| HIGH to OFF-state propagation delay tPHZ | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 5.0 V ± 0.5 V; DIR to A | min 2.7 · max 20.6 ns | 12 |
| HIGH to OFF-state propagation delay tPHZ | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 1.5 V ± 0.1 V; DIR to B | min 3.1 · max 27.3 ns | 12 |
| HIGH to OFF-state propagation delay tPHZ | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 1.8 V ± 0.15 V; DIR to B | min 3.1 · max 26 ns | 12 |
| HIGH to OFF-state propagation delay tPHZ | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 2.5 V ± 0.2 V; DIR to B | min 2.7 · max 12.1 ns | 12 |
| HIGH to OFF-state propagation delay tPHZ | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 3.3 V ± 0.3 V; DIR to B | min 2.9 · max 12.5 ns | 12 |
| HIGH to OFF-state propagation delay tPHZ | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 5.0 V ± 0.5 V; DIR to B | min 2.5 · max 11.4 ns | 12 |
| LOW to OFF-state propagation delay tPLZ | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 1.5 V ± 0.1 V; DIR to A | min 2.1 · max 12.6 ns | 12 |
| LOW to OFF-state propagation delay tPLZ | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 1.8 V ± 0.15 V; DIR to A | min 2.1 · max 12.6 ns | 12 |
| LOW to OFF-state propagation delay tPLZ | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 2.5 V ± 0.2 V; DIR to A | min 2.1 · max 12.6 ns | 12 |
| LOW to OFF-state propagation delay tPLZ | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 3.3 V ± 0.3 V; DIR to A | min 2.1 · max 12.6 ns | 12 |
| LOW to OFF-state propagation delay tPLZ | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 5.0 V ± 0.5 V; DIR to A | min 2.1 · max 12.6 ns | 12 |
| LOW to OFF-state propagation delay tPLZ | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 1.5 V ± 0.1 V; DIR to B | min 2.5 · max 20.2 ns | 12 |
| LOW to OFF-state propagation delay tPLZ | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 1.8 V ± 0.15 V; DIR to B | min 2.7 · max 19 ns | 12 |
| LOW to OFF-state propagation delay tPLZ | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 2.5 V ± 0.2 V; DIR to B | min 2.2 · max 10.4 ns | 12 |
| LOW to OFF-state propagation delay tPLZ | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 3.3 V ± 0.3 V; DIR to B | min 2.7 · max 11.2 ns | 12 |
| LOW to OFF-state propagation delay tPLZ | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 5.0 V ± 0.5 V; DIR to B | min 2.2 · max 10.4 ns | 12 |
| OFF-state to HIGH propagation delay tPZH | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 1.5 V ± 0.1 V; DIR to A; [1] | max 43.7 ns | 12 |
| OFF-state to HIGH propagation delay tPZH | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 1.8 V ± 0.15 V; DIR to A; [1] | max 40.1 ns | 12 |
| OFF-state to HIGH propagation delay tPZH | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 2.5 V ± 0.2 V; DIR to A; [1] | max 26.8 ns | 12 |
| OFF-state to HIGH propagation delay tPZH | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 3.3 V ± 0.3 V; DIR to A; [1] | max 24.9 ns | 12 |
| OFF-state to HIGH propagation delay tPZH | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 5.0 V ± 0.5 V; DIR to A; [1] | max 23.6 ns | 12 |
| OFF-state to HIGH propagation delay tPZH | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 1.5 V ± 0.1 V; DIR to B; [1] | max 36.1 ns | 12 |
| OFF-state to HIGH propagation delay tPZH | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 1.8 V ± 0.15 V; DIR to B; [1] | max 32 ns | 12 |
| OFF-state to HIGH propagation delay tPZH | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 2.5 V ± 0.2 V; DIR to B; [1] | max 27.5 ns | 12 |
| OFF-state to HIGH propagation delay tPZH | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 3.3 V ± 0.3 V; DIR to B; [1] | max 25.6 ns | 12 |
| OFF-state to HIGH propagation delay tPZH | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 5.0 V ± 0.5 V; DIR to B; [1] | max 24.2 ns | 12 |
| OFF-state to LOW propagation delay tPZL | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 1.5 V ± 0.1 V; DIR to A; [1] | max 48.6 ns | 12 |
| OFF-state to LOW propagation delay tPZL | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 1.8 V ± 0.15 V; DIR to A; [1] | max 45.1 ns | 12 |
| OFF-state to LOW propagation delay tPZL | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 2.5 V ± 0.2 V; DIR to A; [1] | max 26.7 ns | 12 |
| OFF-state to LOW propagation delay tPZL | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 3.3 V ± 0.3 V; DIR to A; [1] | max 25 ns | 12 |
| OFF-state to LOW propagation delay tPZL | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 5.0 V ± 0.5 V; DIR to A; [1] | max 23.5 ns | 12 |
| OFF-state to LOW propagation delay tPZL | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 1.5 V ± 0.1 V; DIR to B; [1] | max 41.9 ns | 12 |
| OFF-state to LOW propagation delay tPZL | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 1.8 V ± 0.15 V; DIR to B; [1] | max 37.5 ns | 12 |
| OFF-state to LOW propagation delay tPZL | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 2.5 V ± 0.2 V; DIR to B; [1] | max 33.6 ns | 12 |
| OFF-state to LOW propagation delay tPZL | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 3.3 V ± 0.3 V; DIR to B; [1] | max 32.6 ns | 12 |
| OFF-state to LOW propagation delay tPZL | VCC(A) = 1.4 V to 1.6 V; VCC(B) = 5.0 V ± 0.5 V; DIR to B; [1] | max 32.5 ns | 12 |
Pins, by the datasheet
8- 1 VCC(A)
- Supply voltage A for port A and DIR. · p. 3
- 2 1A
- Data input or output. · p. 3
- 3 2A
- Data input or output. · p. 3
- 4 GND
- Ground (0 V). · p. 3
- 5 DIR
- Direction control. · p. 3
- 6 2B
- Data input or output. · p. 3
- 7 1B
- Data input or output. · p. 3
- 8 VCC(B)
- Supply voltage B for port B. · p. 3
Ordering codes, by the datasheet
9- 74LVC2T45DC
- VSSOP8 · SOT765-1; 8 leads; body width 2.3 mm; -40 °C to +125 °C; without bus hold · p. 2
- 74LVCH2T45DC
- VSSOP8 · SOT765-1; 8 leads; body width 2.3 mm; -40 °C to +125 °C; with bus hold · p. 2
- 74LVC2T45GT
- XSON8 · SOT833-1; 8 terminals; body 1 × 1.95 × 0.5 mm; -40 °C to +125 °C; without bus hold · p. 2
- 74LVCH2T45GT
- XSON8 · SOT833-1; 8 terminals; body 1 × 1.95 × 0.5 mm; -40 °C to +125 °C; with bus hold · p. 2
- 74LVC2T45GF
- XSON8 · SOT1089; 8 terminals; body 1.35 × 1 × 0.5 mm; -40 °C to +125 °C; without bus hold · p. 2
- 74LVC2T45GN
- XSON8 · SOT1116; 8 terminals; body 1.2 × 1.0 × 0.35 mm; -40 °C to +125 °C; without bus hold · p. 2
- 74LVCH2T45GN
- XSON8 · SOT1116; 8 terminals; body 1.2 × 1.0 × 0.35 mm; -40 °C to +125 °C; with bus hold · p. 2
- 74LVC2T45GS
- XSON8 · SOT1203; 8 terminals; body 1.35 × 1.0 × 0.35 mm; -40 °C to +125 °C; without bus hold · p. 2
- 74LVCH2T45GS
- XSON8 · SOT1203; 8 terminals; body 1.35 × 1.0 × 0.35 mm; -40 °C to +125 °C; with bus hold · p. 2
- 4 layers53 × 42 mm
MioLink
Misaka0x2730/MioLink
ARM JTAG/SWD debugger (BlackMagic port) based on RP2040.
117 parts30GPL-3.0 - 2 layers46.2 × 83 mm
PregnantLaserMouse
Board-Folk/PregnantLaserMouse
A optical mouse replacement pcb for the Amiga pregnant mouse
28 parts21 - 2 layers57.9 × 39.9 mm
MCU Link MR
ErichStyger/MCU-Link-MR
Open Source MCU-Link CMSIS-DAP Debug probe for mobile robots (e.g. Pixhawk)
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- 4 layers50 × 35.5 mm
- 4 layers165.6 × 125.5 mm
SparkPNT GNSSDO Plus panelized
sparkfun/SparkFun_GNSSDO
The SparkFun GNSS Disciplined Oscillator (GNSSDO / GNSSDO+) is a precision time and frequency reference based on the Septentrio mosaic-T GNSS receiver.
478 parts6 - 4 layers43.2 × 48.8 mm
DAC peripherals
DamienMorlier/ScanProcessingFPGA
Copyright (c) 2023 Damien Morlier Lin Yudong Morgan Adamsson Samuel Svensson Matteo Rodriguez Derek Holzer
35 parts4MIT
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Questions
Is there a KiCad symbol and footprint for the 74LVC2T45DC?
Yes. The symbol is Logic_LevelTranslator:74LVC2T45DC and the footprint Package_SO:VSSOP-8_3x3mm_P0.65mm, both drawn on this page. PCBKit places them on a board for you when you design with it.
What package is the 74LVC2T45DC?
VSSOP-8-0.5mm, with 8 pins. Its footprint is drawn on this page.
Where is the 74LVC2T45DC datasheet?
Nexperia publishes it: the Datasheet link on this page opens it.
Where can I order the 74LVC2T45DC?
JLCPCB lists it as part C730237, with 55,172 in stock; the sellers' links on this page open their listings.
What can replace the 74LVC2T45DC?
Parts like it in the library: the TCA9517ADGKR by Texas Instruments, the RS0102YVS8 by Jiangsu RUNIC Tech, the LSF0102DCH by Nexperia and the TCA9617BDGK by Texas Instruments. Check their datasheets: a part that fits the footprint may still differ in its ratings.
Which open-source boards use the 74LVC2T45DC?
47 boards in 40 repositories on GitHub; the most starred are listed on this page, with their KiCad files.