LAN9252I/ML

Microchip Technology

-40℃~+85℃ 1.8V~3.3V 100Mbit/s 10BASE-T、100BASE-TX QFN-64-EP(9x9) Ethernet Transceivers ROHS

Extended

Datasheetmicrochip/LAN9252I/ML

Category: Ethernet Transceivers
Package: QFN-64-EP(9x9)
Pins: 65

Overview

The LAN9252I/ML is an ethernet Transceiver made by Microchip Technology in a QFN-64-EP(9x9) package with 65 pins. -40℃~+85℃ 1.8V~3.3V 100Mbit/s 10BASE-T、100BASE-TX QFN-64-EP(9x9) Ethernet Transceivers ROHS.

PCBKit's library has its KiCad symbol (EasyEDA_Cloud:LAN9252T_ML, from EasyEDA) and its footprint (EasyEDA_Cloud:QFN-64_L9.0-W9.0-P0.50-BL-EP7.2, from EasyEDA), ready for a KiCad board. 8,124 are in stock at JLCPCB (part C2758355). 3 open-source boards in 2 repositories on GitHub use it.

Symbol

EasyEDA_Cloud:LAN9252T_MLFrom EasyEDA

Footprint

EasyEDA_Cloud:QFN-64_L9.0-W9.0-P0.50-BL-EP7.2From EasyEDA

From the datasheet

Supply, least: 1.14 V · VDD12TX1, VDD12TX2, OSCVDD12, VDDCR, recommended operating min · p. 307
Supply, most: 1.26 V · VDD12TX1, VDD12TX2, OSCVDD12, VDDCR, recommended operating max · p. 307
Supply, least: 3 V · VDD33TXRX1, VDD33TXRX2, VDD33BIAS, VDD33, recommended operating min · p. 307
Supply, most: 3.6 V · VDD33TXRX1, VDD33TXRX2, VDD33BIAS, VDD33, recommended operating max · p. 307
Supply, absolute maximum: 1.5 V · VDD12TX1, VDD12TX2, OSCVDD12, VDDCR, absolute max · p. 307
Supply, absolute maximum: 3.6 V · VDD33TXRX1, VDD33TXRX2, VDD33BIAS, VDD33, VDDIO, absolute max · p. 307
Works from: -40 °C · Industrial ambient operating min · p. 307
Works up to: 85 °C · Industrial ambient operating max · p. 307
Junction, hottest: 150 °C · Junction temperature absolute max · p. 307
Takes working: 112 mA · Typical 3.3 V device current, D0 100BASE-TX with traffic, regulators enabled; excludes magnetics and LEDs · p. 310
Takes working: 109.7 mA · sum of typical 3.3 V and 1.2 V device currents, D0 100BASE-TX with traffic, regulators disabled; excludes magnetics and LEDs · p. 309
Takes asleep: 4.3 mA · Typical D3 PHY general power down, both PHYs, regulators enabled · p. 310
Takes asleep: 4.2 mA · sum of typical 3.3 V and 1.2 V device currents, D3 PHY general power down, both PHYs, regulators disabled · p. 309
Junction to air (64-PIN QFN): 23.6 K/W · Junction to ambient, still air · p. 308
Junction to case (64-PIN QFN): 1.8 K/W · Junction to top of case, airflow 1 m/s · p. 308
Supply, least: 1.62 V · VDDIO, recommended operating min · p. 307
Supply, least: 2.25 V · Ethernet Magnetics, recommended operating min · p. 307
Takes working: 191.7 mA · sum of 3.3 V, 1.2 V and TX magnetics currents, typical D0 100BASE-TX with traffic, regulator disabled · p. 309
Takes working: 194 mA · sum of 3.3 V and TX magnetics currents, typical D0 100BASE-TX with traffic, regulator enabled · p. 310

What it is and has

Controller: 2/3-port EtherCAT slave controller · p. 1
FMMU: 3 · p. 1
SyncManagers: 4 · p. 1
Dual-port RAM: 4K bytes · p. 1
Host bus interface: 8/16-bit · p. 1
Serial interface: SPI / Quad SPI · p. 1
SPI clock: Up to 80 MHz; single, dual and quad bit lanes · p. 8
Digital I/O: 16 signals · p. 8
Ethernet PHY: HP Auto-MDIX · p. 1
Fiber support: 100BASE-FX via external fiber transceiver · p. 1
Wake on LAN: Supported · p. 1
Cable diagnostics: Supported · p. 1
Power management: 3 power-down levels · p. 1
I/O voltage: 1.8V to 3.3V variable voltage I/O · p. 1
Internal regulator: 1.2V for single 3.3V operation · p. 1
Reset: Integrated power-on reset circuit · p. 1
ESD performance: JEDEC Class 3A · p. 1
GPIO: Multifunction GPIOs · p. 1
Crystal: 25MHz · p. 1
Package: 64-pin QFN · p. 327
EtherCAT ports: 2/3 · p. 1
Ethernet transceivers: Integrated, 100Mbps · p. 1
FMMUs: 3 · p. 1
Ethernet PHYs: Integrated, HP Auto-MDIX · p. 1
I/O voltage: 1.8V to 3.3V variable voltage · p. 1

Around it

cap 1 µF: between VDDCR (pin 6) and VSS; Parallel with 470 pF decoupling capacitor. · p. 28
cap 470 pF: between VDDCR (pin 6) and VSS; Parallel with 1 uF decoupling capacitor. · p. 28
cap 1.0 uF: between VDDCR (pin 6) and VSS; Core regulator capacitor; 0.1 Ω ESR. · p. 31
crystal 25 MHz: between OSCI and OSCO; Alternatively use a single-ended oscillator on OSCI and leave OSCO unconnected. · p. 320

Specifications

244

Parameter	Conditions	As printed	Page
Supply Voltage	VDD12TX1, VDD12TX2, OSCVDD12, VDDCR; Note 1	min 0 · max 1.5 V	307
Supply Voltage	VDD33TXRX1, VDD33TXRX2, VDD33BIAS, VDD33, VDDIO; Note 1	min 0 · max 3.6 V	307
Ethernet Magnetics Supply Voltage		min -0.5 · max 3.6 V	307
Negative voltage on input signal pins, with respect to ground	Note 3; excludes RBIAS	min -0.5 V	307
Positive voltage on OSCI, with respect to ground		max 3.6 V	307
Storage Temperature		min -55 · max 150 oC	307
Junction Temperature		max 150 oC	307
Supply Voltage	VDD12TX1, VDD12TX2, OSCVDD12, VDDCR	min 1.14 · max 1.26 V	307
Analog Port Supply Voltage	VDD33TXRX1, VDD33TXRX2, VDD33BIAS, VDD33	min 3 · max 3.6 V	307
I/O Supply Voltage	VDDIO; Note 1	min 1.62 · max 3.6 V	307
Ethernet Magnetics Supply Voltage		min 2.25 · max 3.6 V	307
Ambient Operating Temperature in Still Air TA	Industrial version	min -40 · max 85 oC	307
Thermal Resistance Junction to Ambient JA	64-PIN QFN; Measured in still air	typ 23.6 °C/W	308
Thermal Resistance Junction to Bottom of Case JT	64-PIN QFN; Measured in still air	typ 0.1 °C/W	308
Thermal Resistance Junction to Top of Case JC	64-PIN QFN; Airflow 1 m/s	typ 1.8 °C/W	308
Maximum Power	Internal Regulator Disabled, 2.5 V Ethernet Magnetics	max 568 mW	308
Maximum Power	Internal Regulator Disabled, 3.3 V Ethernet Magnetics	max 640 mW	308
Maximum Power	Internal Regulator Enabled, 2.5 V Ethernet Magnetics	max 749 mW	308
Maximum Power	Internal Regulator Enabled, 3.3 V Ethernet Magnetics	max 821 mW	308
3.3 V Device Current	Reset (RST#)	typ 23.6 mA	309
1.2 V Device Current	Reset (RST#)	typ 28.3 mA	309
TX Magnetics Current	Reset (RST#)	typ 0 mA	309
Device Power with 2.5 V Magnetics	Reset (RST#)	typ 112 mW	309
Device Power with 3.3 V Magnetics	Reset (RST#)	typ 112 mW	309
3.3 V Device Current	D0, 100BASE-TX with Traffic	typ 58.7 mA	309
1.2 V Device Current	D0, 100BASE-TX with Traffic	typ 51 mA	309
TX Magnetics Current	D0, 100BASE-TX with Traffic	typ 82 mA	309
Device Power with 2.5 V Magnetics	D0, 100BASE-TX with Traffic	typ 461 mW	309
Device Power with 3.3 V Magnetics	D0, 100BASE-TX with Traffic	typ 526 mW	309
3.3 V Device Current	D0, 100BASE-TX Idle	typ 63.4 mA	309
1.2 V Device Current	D0, 100BASE-TX Idle	typ 49.9 mA	309
TX Magnetics Current	D0, 100BASE-TX Idle	typ 82 mA	309
Device Power with 2.5 V Magnetics	D0, 100BASE-TX Idle	typ 475 mW	309
Device Power with 3.3 V Magnetics	D0, 100BASE-TX Idle	typ 540 mW	309
3.3 V Device Current	D0, PHY Energy Detect Power Down (both PHYs)	typ 7.9 mA	309
1.2 V Device Current	D0, PHY Energy Detect Power Down (both PHYs)	typ 30.8 mA	309
TX Magnetics Current	D0, PHY Energy Detect Power Down (both PHYs)	typ 0 mA	309
Device Power with 2.5 V Magnetics	D0, PHY Energy Detect Power Down (both PHYs)	typ 64 mW	309
Device Power with 3.3 V Magnetics	D0, PHY Energy Detect Power Down (both PHYs)	typ 63 mW	309
3.3 V Device Current	D0, PHY General Power Down (both PHYs)	typ 1.5 mA	309
1.2 V Device Current	D0, PHY General Power Down (both PHYs)	typ 30.6 mA	309
TX Magnetics Current	D0, PHY General Power Down (both PHYs)	typ 0 mA	309
Device Power with 2.5 V Magnetics	D0, PHY General Power Down (both PHYs)	typ 42 mW	309
Device Power with 3.3 V Magnetics	D0, PHY General Power Down (both PHYs)	typ 42 mW	309
3.3 V Device Current	D1, 100BASE-TX Idle	typ 63.4 mA	309
1.2 V Device Current	D1, 100BASE-TX Idle	typ 37.5 mA	309
TX Magnetics Current	D1, 100BASE-TX Idle	typ 82 mA	309
Device Power with 2.5 V Magnetics	D1, 100BASE-TX Idle	typ 460 mW	309
Device Power with 3.3 V Magnetics	D1, 100BASE-TX Idle	typ 525 mW	309
3.3 V Device Current	D1, PHY Energy Detect Power Down (both PHYs)	typ 7.8 mA	309
1.2 V Device Current	D1, PHY Energy Detect Power Down (both PHYs)	typ 17.6 mA	309
TX Magnetics Current	D1, PHY Energy Detect Power Down (both PHYs)	typ 0 mA	309
Device Power with 2.5 V Magnetics	D1, PHY Energy Detect Power Down (both PHYs)	typ 47 mW	309
Device Power with 3.3 V Magnetics	D1, PHY Energy Detect Power Down (both PHYs)	typ 47 mW	309
3.3 V Device Current	D1, PHY General Power Down (both PHYs)	typ 1.5 mA	309
1.2 V Device Current	D1, PHY General Power Down (both PHYs)	typ 17.7 mA	309
TX Magnetics Current	D1, PHY General Power Down (both PHYs)	typ 0 mA	309
Device Power with 2.5 V Magnetics	D1, PHY General Power Down (both PHYs)	typ 27 mW	309
Device Power with 3.3 V Magnetics	D1, PHY General Power Down (both PHYs)	typ 27 mW	309
3.3 V Device Current	D2, 100BASE-TX Idle	typ 63.4 mA	309
1.2 V Device Current	D2, 100BASE-TX Idle	typ 37.5 mA	309
TX Magnetics Current	D2, 100BASE-TX Idle	typ 82 mA	309
Device Power with 2.5 V Magnetics	D2, 100BASE-TX Idle	typ 460 mW	309
Device Power with 3.3 V Magnetics	D2, 100BASE-TX Idle	typ 525 mW	309
3.3 V Device Current	D2, PHY Energy Detect Power Down (both PHYs)	typ 7.8 mA	309
1.2 V Device Current	D2, PHY Energy Detect Power Down (both PHYs)	typ 6.3 mA	309
TX Magnetics Current	D2, PHY Energy Detect Power Down (both PHYs)	typ 0 mA	309
Device Power with 2.5 V Magnetics	D2, PHY Energy Detect Power Down (both PHYs)	typ 34 mW	309
Device Power with 3.3 V Magnetics	D2, PHY Energy Detect Power Down (both PHYs)	typ 34 mW	309
3.3 V Device Current	D2, PHY General Power Down (both PHYs)	typ 1.5 mA	309
1.2 V Device Current	D2, PHY General Power Down (both PHYs)	typ 6.1 mA	309
TX Magnetics Current	D2, PHY General Power Down (both PHYs)	typ 0 mA	309
Device Power with 2.5 V Magnetics	D2, PHY General Power Down (both PHYs)	typ 13 mW	309
Device Power with 3.3 V Magnetics	D2, PHY General Power Down (both PHYs)	typ 13 mW	309
3.3 V Device Current	D3, PHY General Power Down (both PHYs)	typ 1.5 mA	309
1.2 V Device Current	D3, PHY General Power Down (both PHYs)	typ 2.7 mA	309
TX Magnetics Current	D3, PHY General Power Down (both PHYs)	typ 0 mA	309
Device Power with 2.5 V Magnetics	D3, PHY General Power Down (both PHYs)	typ 9 mW	309
Device Power with 3.3 V Magnetics	D3, PHY General Power Down (both PHYs)	typ 9 mW	309
3.3 V Device Current	Reset (RST#)	typ 51.2 mA	310
TX Magnetics Current	Reset (RST#)	typ 0 mA	310
Device Power with 2.5 V Magnetics	Reset (RST#)	typ 169 mW	310
Device Power with 3.3 V Magnetics	Reset (RST#)	typ 169 mW	310
3.3 V Device Current	D0, 100BASE-TX with Traffic	typ 112 mA	310
TX Magnetics Current	D0, 100BASE-TX with Traffic	typ 82 mA	310
Device Power with 2.5 V Magnetics	D0, 100BASE-TX with Traffic	typ 576 mW	310
Device Power with 3.3 V Magnetics	D0, 100BASE-TX with Traffic	typ 642 mW	310
3.3 V Device Current	D0, 100BASE-TX Idle	typ 113.5 mA	310
TX Magnetics Current	D0, 100BASE-TX Idle	typ 82 mA	310
Device Power with 2.5 V Magnetics	D0, 100BASE-TX Idle	typ 580 mW	310
Device Power with 3.3 V Magnetics	D0, 100BASE-TX Idle	typ 646 mW	310
3.3 V Device Current	D0, PHY Energy Detect Power Down (both PHYs)	typ 39.7 mA	310
TX Magnetics Current	D0, PHY Energy Detect Power Down (both PHYs)	typ 0 mA	310
Device Power with 2.5 V Magnetics	D0, PHY Energy Detect Power Down (both PHYs)	typ 132 mW	310
Device Power with 3.3 V Magnetics	D0, PHY Energy Detect Power Down (both PHYs)	typ 132 mW	310
3.3 V Device Current	D0, PHY General Power Down (both PHYs)	typ 33 mA	310
TX Magnetics Current	D0, PHY General Power Down (both PHYs)	typ 0 mA	310
Device Power with 2.5 V Magnetics	D0, PHY General Power Down (both PHYs)	typ 109 mW	310
Device Power with 3.3 V Magnetics	D0, PHY General Power Down (both PHYs)	typ 109 mW	310
3.3 V Device Current	D1, 100BASE-TX Idle	typ 100.5 mA	310
TX Magnetics Current	D1, 100BASE-TX Idle	typ 82 mA	310
Device Power with 2.5 V Magnetics	D1, 100BASE-TX Idle	typ 537 mW	310
Device Power with 3.3 V Magnetics	D1, 100BASE-TX Idle	typ 603 mW	310
3.3 V Device Current	D1, PHY Energy Detect Power Down (both PHYs)	typ 26 mA	310
TX Magnetics Current	D1, PHY Energy Detect Power Down (both PHYs)	typ 0 mA	310
Device Power with 2.5 V Magnetics	D1, PHY Energy Detect Power Down (both PHYs)	typ 86 mW	310
Device Power with 3.3 V Magnetics	D1, PHY Energy Detect Power Down (both PHYs)	typ 86 mW	310
3.3 V Device Current	D1, PHY General Power Down (both PHYs)	typ 19.4 mA	310
TX Magnetics Current	D1, PHY General Power Down (both PHYs)	typ 0 mA	310
Device Power with 2.5 V Magnetics	D1, PHY General Power Down (both PHYs)	typ 65 mW	310
Device Power with 3.3 V Magnetics	D1, PHY General Power Down (both PHYs)	typ 65 mW	310
3.3 V Device Current	D2, 100BASE-TX Idle	typ 100.5 mA	310
TX Magnetics Current	D2, 100BASE-TX Idle	typ 82 mA	310
Device Power with 2.5 V Magnetics	D2, 100BASE-TX Idle	typ 537 mW	310
Device Power with 3.3 V Magnetics	D2, 100BASE-TX Idle	typ 603 mW	310
3.3 V Device Current	D2, PHY Energy Detect Power Down (both PHYs)	typ 14.8 mA	310
TX Magnetics Current	D2, PHY Energy Detect Power Down (both PHYs)	typ 0 mA	310
Device Power with 2.5 V Magnetics	D2, PHY Energy Detect Power Down (both PHYs)	typ 49 mW	310
Device Power with 3.3 V Magnetics	D2, PHY Energy Detect Power Down (both PHYs)	typ 49 mW	310
3.3 V Device Current	D2, PHY General Power Down (both PHYs)	typ 7.8 mA	310
TX Magnetics Current	D2, PHY General Power Down (both PHYs)	typ 0 mA	310
Device Power with 2.5 V Magnetics	D2, PHY General Power Down (both PHYs)	typ 26 mW	310
Device Power with 3.3 V Magnetics	D2, PHY General Power Down (both PHYs)	typ 26 mW	310
3.3 V Device Current	D3, PHY General Power Down (both PHYs)	typ 4.3 mA	310
TX Magnetics Current	D3, PHY General Power Down (both PHYs)	typ 0 mA	310
Device Power with 2.5 V Magnetics	D3, PHY General Power Down (both PHYs)	typ 15 mW	310
Device Power with 3.3 V Magnetics	D3, PHY General Power Down (both PHYs)	typ 15 mW	310
Low Input Level VILI	IS Type Input Buffer	min -0.3 · max 0.8 V	311
High Input Level VIHI	IS Type Input Buffer	min 2 · max 3.6 V	311
Schmitt Trigger Hysteresis (VIHT - VILT) VHYS	IS Type Input Buffer	min 121 · max 151 mV	311
Input Leakage IIH	IS Type Input Buffer; VIN = VSS or VDD33; Note 19	min -10 · max 10 uA	311
Input Capacitance CIN	IS Type Input Buffer	max 3 pF	311
Pull-Up Impedance RDPU	IS Type Input Buffer; VIN = VSS	min 6 · max 8.9 KΩ	311
Pull-Down Impedance RDPD	IS Type Input Buffer; VIN = VDD33	min 52 · max 79 KΩ	311
Low Input Level VIL	AI Type Input Buffer; FXSDENA/FXSDENB	min -0.3 · max 0.8 V	311
High Input Level VIH	AI Type Input Buffer; FXSDENA/FXSDENB; maximum VDD33+0.3	min 1.2 V	311
Differential Input Level VIN-DIFF	AI Type Input Buffer; RXPA/RXNA/RXPB/RXNB; maximum VDD33TXRXx	min 0.1 V	311
Common Mode Voltage VCM	AI Type Input Buffer; RXPA/RXNA/RXPB/RXNB; typical VDD33TXRXx-1.3	min 1 V	311
Input Capacitance CIN	AI Type Input Buffer; RXPA/RXNA/RXPB/RXNB	max 5 pF	311
State A Threshold VTHA	AI Type Input Buffer; FXLOSEN Input	min -0.3 · max 0.8 V	311
State B Threshold VTHB	AI Type Input Buffer; FXLOSEN Input	min 1.2 · max 1.7 V	311
State C Threshold VTHC	AI Type Input Buffer; FXLOSEN Input; maximum VDD33+0.3	min 2.3 V	311
Low Input Level VILI	ICLK Type Input Buffer; OSCI Input; Note 20	min -0.3 · max 0.35 V	311
High Input Level VIHI	ICLK Type Input Buffer; OSCI Input; minimum OSCVDD12-0.35	max 3.6 V	311
Input Leakage IILCK	ICLK Type Input Buffer; OSCI Input	min -10 · max 10 uA	311
Low Input Level VIL-VDD33TXRXx	ILVPECL Input Buffer; minimum printed as VDD33TXRXx+0.3; Note 21	max -1.48 V	312
High Input Level VIH-VDD33TXRXx	ILVPECL Input Buffer; Note 21	min -1.14 · max 0.3 V	312
Peak-to-Peak Differential VDIFF-SFF	OLVPECL Output Buffer; SFF mode	min 1.2 · typ 1.6 · max 2 V	312
Peak-to-Peak Differential VDIFF-SFP	OLVPECL Output Buffer; SFP mode	min 0.6 · typ 0.8 · max 1 V	312
Common Mode Voltage VCM	OLVPECL Output Buffer; typical VDD33TXRXx-1.3	min 1 V	312
Offset Voltage VOFFSET	OLVPECL Output Buffer; Note 22	typ 40 mV	312
Load Capacitance CLOAD	OLVPECL Output Buffer	max 10 pF	312
Low Input Level VILI	VIS Type Input Buffer	min -0.3 V	313
High Input Level VIHI	VIS Type Input Buffer	max 3.6 V	313
Negative-Going Threshold VILT	VIS Type Input Buffer; 1.8 V typical column; Schmitt trigger	min 0.64 · typ 0.83 · max 1.76 V	313
Negative-Going Threshold VILT	VIS Type Input Buffer; 3.3 V typical column; Schmitt trigger	min 0.64 · typ 1.41 · max 1.76 V	313
Positive-Going Threshold VIHT	VIS Type Input Buffer; 1.8 V typical column; Schmitt trigger	min 0.81 · typ 0.99 · max 1.9 V	313
Positive-Going Threshold VIHT	VIS Type Input Buffer; 3.3 V typical column; Schmitt trigger	min 0.81 · typ 1.65 · max 1.9 V	313
Schmitt Trigger Hysteresis (VIHT - VILT) VHYS	VIS Type Input Buffer; 1.8 V typical column	min 102 · typ 158 · max 288 mV	313
Schmitt Trigger Hysteresis (VIHT - VILT) VHYS	VIS Type Input Buffer; 3.3 V typical column	min 102 · typ 138 · max 288 mV	313
Input Leakage IIH	VIS Type Input Buffer; VIN = VSS or VDDIO; Note 23	min -10 · max 10 uA	313
Input Capacitance CIN	VIS Type Input Buffer	max 2 pF	313
Pull-Up Impedance RDPU	VIS Type Input Buffer; VIN = VSS; 1.8 V typical column	min 54 · typ 68 KΩ	313
Pull-Up Impedance RDPU	VIS Type Input Buffer; VIN = VSS; 3.3 V typical column	min 54 · typ 82 KΩ	313
Pull-Up Current IDPU	VIS Type Input Buffer; VIN = VSS; 1.8 V typical column	min 20 · typ 27 uA	313
Pull-Up Current IDPU	VIS Type Input Buffer; VIN = VSS; 3.3 V typical column	min 20 · typ 67 uA	313
Pull-Down Impedance RDPD	VIS Type Input Buffer; VIN = VDD33; 1.8 V typical column	min 54 · typ 68 KΩ	313
Pull-Down Impedance RDPD	VIS Type Input Buffer; VIN = VDD33; 3.3 V typical column	min 54 · typ 85 KΩ	313
Pull-Down Current IDPD	VIS Type Input Buffer; VIN = VDD33; 1.8 V typical column	min 19 · typ 26 uA	313
Pull-Down Current IDPD	VIS Type Input Buffer; VIN = VDD33; 3.3 V typical column	min 19 · typ 66 uA	313
Low Output Level VOL	VO8 Type Buffers; IOL = 8 mA	max 0.4 V	313
Low Output Level VOL	VOD8 Type Buffer; IOL = 8 mA	max 0.4 V	313
Low Output Level VOL	VO12 Type Buffers; IOL = 12 mA	max 0.4 V	313
Low Output Level VOL	VOD12 Type Buffer; IOL = 12 mA	max 0.4 V	313
Low Output Level VOL	VO16 Type Buffers; IOL = 16 mA	max 0.4 V	313
Peak Differential Output Voltage High VPPH	Note 24; measured at line side of transformer with 100 Ω (+/- 1%) resistor replacing line	min 950 · max 1050 mVpk	314
Peak Differential Output Voltage Low VPPL	Note 24; measured at line side of transformer with 100 Ω (+/- 1%) resistor replacing line	min -950 · max -1050 mVpk	314
Signal Amplitude Symmetry VSS	Note 24	min 98 · max 102 %	314
Signal Rise and Fall Time TRF	Note 24	min 3 · max 5 ns	314
Rise and Fall Symmetry TRFS	Note 24	max 0.5 ns	314
Duty Cycle Distortion DCD	Note 25; offset from 16 ns pulse width at 50% of pulse peak	min 35 · typ 50 · max 65 %	314
Overshoot and Undershoot VOS		max 5 %	314
Jitter	Note 26; measured differentially	max 1.4 ns	314
Frequency Ffund	NOM column	typ 25 MHz	320
802.3 Frequency Tolerance at 25oC Ftol	Maximum ±40 ppm; Note 27	max 40 ppm	320
802.3 Frequency Stability Over Temp Ftemp	Maximum ±40 ppm; Note 27	max 40 ppm	320
802.3 Total Allowable PPM Budget	Maximum ±50 ppm; Note 29	max 50 ppm	320
EtherCAT Frequency Tolerance at 25oC Ftol	Maximum ±15 ppm; Note 30	max 15 ppm	320
EtherCAT Frequency Stability Over Temp Ftemp	Maximum ±15 ppm; Note 30	max 15 ppm	320
EtherCAT Total Allowable PPM Budget	Maximum ±25 ppm; Note 31	max 25 ppm	320
Shunt Capacitance CO		max 7 pF	320
Load Capacitance CL		max 18 pF	320
Drive Level PW	Note 32	min 300 uW	320
Equivalent Series Resistance R1		max 100 Ω	320
OSCI Pin Capacitance	Note 35	typ 3 pF	320
OSCO Pin Capacitance	Note 35	typ 3 pF	320
EESCL clock frequency fscl		typ 148.8 kHz	295
EESCL high time thigh		min 3 s	295
EESCL low time tlow		min 3 s	295
Rise time of EESDA and EESCL tr		max 300 ns	295
Fall time of EESDA and EESCL tf		max 300 ns	295
Setup time (provided to slave) of EESCL high before EESDA output falling for repeated start condition tsu;sta	Note 41	min 1000 ns	295
Hold time (provided to slave) of EESCL after EESDA output falling for start or repeated start condition thd;sta	Note 41	min 1000 ns	295
Setup time (from slave) EESDA input before EESCL rising tsu;dat;in	Note 42	min 200 ns	295
Hold time (from slave) of EESDA input after EESCL falling thd;dat;in		min 0 ns	295
Setup time (provided to slave) EESDA output before EESCL rising tsu;dat;out	Note 42	min 400 ns	295
Hold time (provided to slave) of EESDA output after EESCL falling thd;dat;out	Note 42	min 400 ns	295
Setup time (provided to slave) of EESCL high before EESDA output rising for stop condition tsu;sto	Note 41	min 1000 ns	295
Supply Voltage (VDD12TX1, VDD12TX2, OSCVDD12, VDDCR)	Note 1	min 0 · max 1.5 V	307
Supply Voltage (VDD33TXRX1, VDD33TXRX2, VDD33BIAS, VDD33, VDDIO)	Note 1	min 0 · max 3.6 V	307
Negative voltage on input signal pins, with respect to ground	Excludes RBIAS (Note 3)	min -0.5 V	307
Supply Voltage (VDD12TX1, VDD12TX2, OSCVDD12, VDDCR)		min 1.14 · max 1.26 V	307
Analog Port Supply Voltage (VDD33TXRX1, VDD33TXRX2, VDD33BIAS, VDD33)		min 3 · max 3.6 V	307
Ambient Operating Temperature in Still Air TA	Industrial version; Note 4	min -40 · max 85 oC	307
Thermal Resistance Junction to Ambient JA	Measured in still air	typ 23.6 °C/W	308
Thermal Resistance Junction to Bottom of Case JT	Measured in still air	typ 0.1 °C/W	308
Thermal Resistance Junction to Top of Case JC	Airflow 1 m/s	typ 1.8 °C/W	308
TX Magnetics Current C	D0, 100BASE-TX with Traffic; two copper TP operation	typ 82 mA	309
TX Magnetics Current C	D0, 100BASE-TX Idle; two copper TP operation	typ 82 mA	309
TX Magnetics Current C	D1, 100BASE-TX Idle; two copper TP operation	typ 82 mA	309
TX Magnetics Current C	D2, 100BASE-TX Idle; two copper TP operation	typ 82 mA	309
TX Magnetics Current C	D0, 100BASE-TX with Traffic; two copper TP operation	typ 82 mA	310
TX Magnetics Current C	D0, 100BASE-TX Idle; two copper TP operation	typ 82 mA	310
TX Magnetics Current C	D1, 100BASE-TX Idle; two copper TP operation	typ 82 mA	310
TX Magnetics Current C	D2, 100BASE-TX Idle; two copper TP operation	typ 82 mA	310
Negative-Going Threshold VILT	VIS Type Input Buffer; 1.8 V; Schmitt trigger	min 0.64 · typ 0.83 · max 1.76 V	313
Negative-Going Threshold VILT	VIS Type Input Buffer; 3.3 V; Schmitt trigger	min 0.64 · typ 1.41 · max 1.76 V	313
Positive-Going Threshold VIHT	VIS Type Input Buffer; 1.8 V; Schmitt trigger	min 0.81 · typ 0.99 · max 1.9 V	313
Positive-Going Threshold VIHT	VIS Type Input Buffer; 3.3 V; Schmitt trigger	min 0.81 · typ 1.65 · max 1.9 V	313
Schmitt Trigger Hysteresis (VIHT - VILT) VHYS	VIS Type Input Buffer; 1.8 V	min 102 · typ 158 · max 288 mV	313
Schmitt Trigger Hysteresis (VIHT - VILT) VHYS	VIS Type Input Buffer; 3.3 V	min 102 · typ 138 · max 288 mV	313
Pull-Up Impedance RDPU	VIS Type Input Buffer; VIN = VSS; 1.8 V	min 54 · typ 68 KΩ	313
Pull-Up Impedance RDPU	VIS Type Input Buffer; VIN = VSS; 3.3 V	min 54 · typ 82 KΩ	313
Pull-Up Current IDPU	VIS Type Input Buffer; VIN = VSS; 1.8 V	min 20 · typ 27 uA	313
Pull-Up Current IDPU	VIS Type Input Buffer; VIN = VSS; 3.3 V	min 20 · typ 67 uA	313
Pull-Down Impedance RDPD	VIS Type Input Buffer; VIN = VDD33; 1.8 V	min 54 · typ 68 KΩ	313
Pull-Down Impedance RDPD	VIS Type Input Buffer; VIN = VDD33; 3.3 V	min 54 · typ 85 KΩ	313
Pull-Down Current IDPD	VIS Type Input Buffer; VIN = VDD33; 1.8 V	min 19 · typ 26 uA	313
Pull-Down Current IDPD	VIS Type Input Buffer; VIN = VDD33; 3.3 V	min 19 · typ 66 uA	313
External power supplies at operational level to RST# deassertion tpurstd		min 25 ms	317
RST# input assertion time trstia		min 200 s	317
Configuration strap pins setup to RST# deassertion tcss		min 200 ns	317
Configuration strap pins hold after RST# deassertion tcsh		min 10 ns	317
Output drive after deassertion todad		min 3 us	317

Pins, by the datasheet

1 OSCI: External 25 MHz crystal input; may be driven by a single-ended oscillator with OSCO unconnected. · p. 27
2 OSCO: External 25 MHz crystal output. · p. 27
3 OSCVDD12: Crystal supply, supplied by the on-chip regulator unless regulator off mode is selected. · p. 27
4 OSCVSS: Crystal ground. · p. 27
5 VDD33: +3.3 V regulator supply; required even when internal regulators are disabled. · p. 28
6 VDDCR: Digital core supply from the on-chip regulator or external supply; use parallel 1 uF and 470 pF capacitors to ground. · p. 28
7 REG_EN: Tie to 3.3 V to enable internal regulators or VSS to disable them. · p. 31
8 FXLOSEN: FXLOSEN input. · p. 311
9 FXSDA/FXLOSA/FXSDENA: Mode-dependent FXSDA, FXLOSA or FXSDENA input. · p. 12
10 FXSDB/FXLOSB/FXSDENB: Mode-dependent FXSDB, FXLOSB or FXSDENB input. · p. 12
11 RST#: Active-low external reset input and reset output during POR or an EtherCAT reset command; may be unconnected if external reset is unnecessary. · p. 27
12 D2/AD2/SOF/SIO2: HBI data or address/data bit 2, digital I/O SOF, or SPI SIO2, depending on mode. · p. 11
13 D1/AD1/EOF/SO/SIO1: HBI data or address/data bit 1, digital I/O EOF, or SPI SO/SIO1, depending on mode. · p. 11
14 VDDIO: Variable I/O power supply. · p. 28
15 D14/AD14/DIGIO8/GPI8/GPO8/MII_TXD3/TX_SHIFT1: HBI bit 14, digital I/O 8, GPIO 8, or MII_TXD3/TX_SHIFT1, depending on mode. · p. 11
16 D13/AD13/DIGIO7/GPI7/GPO7/MII_TXD2/TX_SHIFT0: HBI bit 13, digital I/O 7, GPIO 7, or MII_TXD2/TX_SHIFT0, depending on mode. · p. 11
17 D0/AD0/WD_STATE/SI/SIO0: HBI bit 0, digital I/O WD_STATE, or SPI SI/SIO0, depending on mode. · p. 11
18 SYNC1/LATCH1: SYNC1 or LATCH1 function. · p. 12
19 D9/AD9/LATCH_IN/SCK: HBI bit 9, digital I/O LATCH_IN, or SPI SCK, depending on mode. · p. 11
20 VDDIO: Variable I/O power supply. · p. 28
21 D12/AD12/DIGIO6/GPI6/GPO6/MII_TXD1: HBI bit 12, digital I/O 6, GPIO 6, or MII_TXD1, depending on mode. · p. 11
22 D11/AD11/DIGIO5/GPI5/GPO5/MII_TXD0: HBI bit 11, digital I/O 5, GPIO 5, or MII_TXD0, depending on mode. · p. 11
23 D10/AD10/DIGIO4/GPI4/GPO4/MII_TXEN: HBI bit 10, digital I/O 4, GPIO 4, or MII_TXEN, depending on mode. · p. 11
24 VDDCR: Digital core supply from the on-chip regulator or an external supply. · p. 28
25 A1/ALELO/OE_EXT/MII_CLK25: Indexed A1, multiplexed ALELO, digital I/O OE_EXT, or MII_CLK25; unused in SPI with GPIO mode. · p. 11
26 A3/DIGIO11/GPI11/GPO11/MII_RXDV: Indexed A3, digital I/O 11, GPIO 11, or MII_RXDV; unused in multiplexed HBI mode. · p. 11
27 A4/DIGIO12/GPI12/GPO12/MII_RXD0: Indexed A4, digital I/O 12, GPIO 12, or MII_RXD0; unused in multiplexed HBI mode. · p. 11
28 CS/DIGIO13/GPI13/GPO13/MII_RXD1: HBI CS, digital I/O 13, GPIO 13, or MII_RXD1, depending on mode. · p. 11
30 WR/ENB/DIGIO14/GPI14/GPO14/MII_RXD2: HBI WR/ENB, digital I/O 14, GPIO 14, or MII_RXD2, depending on mode. · p. 11
31 RD/RD_WR/DIGIO15/GPI15/GPO15/MII_RXD3: HBI RD/RD_WR, digital I/O 15, GPIO 15, or MII_RXD3, depending on mode. · p. 11
32 VDDIO: Variable I/O power supply. · p. 28
33 A0/D15/AD15/DIGIO9/GPI9/GPO9/MII_RXER: Indexed A0/D15, multiplexed AD15, digital I/O 9, GPIO 9, or MII_RXER, depending on mode. · p. 11
34 SYNC0/LATCH0: SYNC0 or LATCH0 function. · p. 13
35 D3/AD3/WD_TRIG/SIO3: HBI bit 3, digital I/O WD_TRIG, or SPI SIO3, depending on mode. · p. 11
36 D6/AD6/DIGIO0/GPI0/GPO0/MII_RXCLK: HBI bit 6, digital I/O 0, GPIO 0, or MII_RXCLK, depending on mode. · p. 11
37 VDDIO: Variable I/O power supply. · p. 28
38 VDDCR: Digital core supply from the on-chip regulator or an external supply. · p. 28
39 D7/AD7/DIGIO1/GPI1/GPO1/MII_MDC: HBI bit 7, digital I/O 1, GPIO 1, or MII_MDC, depending on mode. · p. 11
40 D8/AD8/DIGIO2/GPI2/GPO2/MII_MDIO: HBI bit 8, digital I/O 2, GPIO 2, or MII_MDIO, depending on mode. · p. 11
41 TESTMODE: Must be tied to VSS for proper operation. · p. 27
42 EESDA/TMS: EESDA or JTAG test mode select. · p. 13
43 EESCL/TCK: EESCL or JTAG test clock. · p. 13
44 IRQ: Interrupt request output with programmable polarity, source and buffer type. · p. 27
45 RUNLED/E2PSIZE: RUNLED or E2PSIZE function. · p. 13
46 LINKACTLED1/TDI/CHIP_MODE1: LINKACTLED1, JTAG data input, or CHIP_MODE1 function. · p. 13
47 VDDIO: Variable I/O power supply. · p. 28
48 LINKACTLED0/TDO/CHIP_MODE0: Port 0 link/activity LED output, JTAG data output, or chip mode strap; LED drive and polarity depend on the reset strap. · p. 11
49 D4/AD4/DIGIO3/GPI3/GPO3/MII_LINK: HBI bit 4, digital I/O 3, GPIO 3, or MII_LINK, depending on mode. · p. 11
50 D5/AD5/OUTVALID/SCS#: HBI bit 5, digital I/O OUTVALID, or SPI SCS#, depending on mode. · p. 11
51 VDD33TXRX1: Analog port supply. · p. 307
52 TXNA: TXNA connection. · p. 13
53 TXPA: TXPA connection. · p. 13
54 RXNA: Differential analog receive input. · p. 311
55 RXPA: Differential analog receive input. · p. 311
56 VDD12TX1: 1.2 V supply, driven by the internal regulator via the PCB when enabled. · p. 310
57 RBIAS: RBIAS connection. · p. 13
58 VDD33BIAS: Analog port supply. · p. 307
59 VDD12TX2: 1.2 V supply, driven by the internal regulator via the PCB when enabled. · p. 310
60 RXPB: Differential analog receive input. · p. 311
61 RXNB: Differential analog receive input. · p. 311
62 TXPB: TXPB connection. · p. 13
63 TXNB: TXNB connection. · p. 13
64 VDD33TXRX2: Analog port supply. · p. 307
Exposed Pad VSS: Common ground; connect the exposed pad to the ground plane with a via array. · p. 28

Ordering codes, by the datasheet

LAN9252/ML: 64-pin QFN · Commercial temperature; standard packaging (tray). · p. 327
LAN9252TI/PT: 64-pin TQFP-EP · Industrial temperature; tape and reel. · p. 327

Parameters

Current - Supply: 112mA
Data Rate: 100Mbit/s
Ethernet Speed Standards: 100BASE-TX
Features: SupportEtherCAT
Junction Temperature(Max): 150℃
MAC Interface: MII
Number of ports: 2
Operating Temperature: -40℃~+85℃
Standby Current: 4.3mA
Thermal Resistance(Junction to Ambient): 23.6℃/W
Thermal Resistance(Junction to Case): 1.8℃/W
Voltage - Supply: 1.14V~3.6V
Voltage - Supply(Absolute Max): 1.5V

Order codes

LAN9252I/MLLCSC C2758355

Pinout

The pins of the LAN9252I/ML
Pin	Name	Type
1	OSCI	Unspecified
2	OSCO	Unspecified
3	OSCVDD12	Unspecified
4	OSCVSS	Unspecified
5	VDD33	Unspecified
6	VDDCR	Unspecified
7	REG_EN	Unspecified
8	FXLOSEN	Unspecified
9	FXSDA/FXLOSA/FXSDENA	Unspecified
10	FXSDB/FXLOSB/FXSDENB	Unspecified
11	RST#	Unspecified
12	D2/AD2/SOF/SIO2	Unspecified
13	D1/AD1/EOF/SO/SIO1	Unspecified
14	VDDIO	Unspecified
15	D14/AD14/DIGIO8/GPI8/GPO8/MII_TXD3/TX_SHIFT1	Unspecified
16	D13/AD13/DIGIO7/GPI7/GPO7/MII_TXD2/TX_SHIFT0	Unspecified
17	D0/AD0/WD_STATE/SI/SIO0	Unspecified
18	SYNC1/LATCH1	Unspecified
19	D9/AD9/LATCH_IN/SCK	Unspecified
20	VDDIO	Unspecified
21	D12/AD12/DIGIO6/GPI6/GPO6/MII_TXD1	Unspecified
22	D11/AD11/DIGIO5/GPI5/GPO5/MII_TXD0	Unspecified
23	D10/AD10/DIGIO4/GPI4/GPO4/MII_TXEN	Unspecified
24	VDDCR	Unspecified
25	A1/ALELO/OE_EXT/MII_CLK25	Unspecified
26	A3/DIGIO11/GPI11/GPO11/MII_RXDV	Unspecified
27	A4/DIGIO12/GPI12/GPO12/MII_RXD0	Unspecified
28	CS/DIGIO13/GPI13/GPO13/MII_RXD1	Unspecified
29	A2/ALEHI/DIGIO10/GPI10/GPO10/LINKACTLED2/MII_LINKPOL	Unspecified
30	WR/ENB/DIGIO14/GPI14/GPO14/MII_RXD2	Unspecified
31	RD/RD_WR/DIGIO15/GPI15/GPO15/MII_RXD3	Unspecified
32	VDDIO	Unspecified
33	A0/D15/AD15/DIGIO9/GPI9/GPO9/MII_RXER	Unspecified
34	SYNC0/LATCH0	Unspecified
35	D3/AD3/WD_TRIG/SIO3	Unspecified
36	D6/AD6/DIGIO0/GPI0/GPO0/MII_RXCLK	Unspecified
37	VDDIO	Unspecified
38	VDDCR	Unspecified
39	D7/AD7/DIGIO1/GPI1/GPO1/MII_MDC	Unspecified
40	D8/AD8/DIGIO2/GPI2/GPO2/MII_MDIO	Unspecified
41	TESTMODE	Unspecified
42	EESDA/TMS	Unspecified
43	EESCL/TCK	Unspecified
44	IRQ	Unspecified
45	RUNLED/E2PSIZE	Unspecified
46	LINKACTLED1/TDI/CHIP_MODE1	Unspecified
47	VDDIO	Unspecified
48	LINKACTLED0/TDO/CHIP_MODE0	Unspecified
49	D4/AD4/DIGIO3/GPI3/GPO3/MII_LINK	Unspecified
50	D5/AD5/OUTVALID/SCS#	Unspecified
51	VDD33TXRX1	Unspecified
52	TXNA	Unspecified
53	TXPA	Unspecified
54	RXNA	Unspecified
55	RXPA	Unspecified
56	VDD12TX1	Unspecified
57	RBIAS	Unspecified
58	VDD33BIAS	Unspecified
59	VDD12TX2	Unspecified
60	RXPB	Unspecified
61	RXNB	Unspecified
62	TXPB	Unspecified
63	TXNB	Unspecified
64	VDD33TXRX2	Unspecified
65	EP	Unspecified

Open-source boards using it

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Questions

Is there a KiCad symbol and footprint for the LAN9252I/ML?

Yes. The symbol is EasyEDA_Cloud:LAN9252T_ML and the footprint EasyEDA_Cloud:QFN-64_L9.0-W9.0-P0.50-BL-EP7.2, both drawn on this page. PCBKit places them on a board for you when you design with it.

What package is the LAN9252I/ML?

QFN-64-EP(9x9), with 65 pins. Its footprint is drawn on this page.

Where is the LAN9252I/ML datasheet?

Microchip Technology publishes it: the Datasheet link on this page opens it.

Where can I order the LAN9252I/ML?

JLCPCB lists it as part C2758355, with 8,124 in stock; the sellers' links on this page open their listings.

Which open-source boards use the LAN9252I/ML?

3 boards in 2 repositories on GitHub; the most starred are listed on this page, with their KiCad files.