
AP64501SP
Diodes IncorporatedExtended
-40℃~+85℃ 1 25uA 3.8V~40V 570kHz 5A 800mV~39V Adjustable Buck Built-in Overcurrent Protection、Light load efficient mode、Adjustable soft-start、Cycle-by-cycle current limiting、Hiccup current limiting、External compensation、EMI optimization (spread spectrum) Step-down type Yes SOIC-8-EP DC-DC Converters ROHS
- Part id
- diodes/AP64501SP
- Category
- DC DC Converters
- Package
- SOIC-8-EP
- Pins
- 9
- In stock
- 1 at JLCPCB (C2071517)
- Used on
- 1 open-source board
Overview
The AP64501SP is a DC DC Converter made by Diodes Incorporated in a SOIC-8-EP package with 9 pins. -40℃~+85℃ 1 25uA 3.8V~40V 570kHz 5A 800mV~39V Adjustable Buck Built-in Overcurrent Protection、Light load efficient mode、Adjustable soft-start、Cycle-by-cycle current limiting、Hiccup current limiting、External compensation、EMI optimization (spread spectrum) Step-down type Yes SOIC-8-EP DC-DC Converters ROHS.
PCBKit's library has its KiCad symbol (EasyEDA_Cloud:AP64351SP-13, from EasyEDA) and its footprint (EasyEDA_Cloud:SOIC-8_L4.9-W3.9-P1.27-LS6.0-BL-EP-1, from EasyEDA), ready for a KiCad board. 1 are in stock at JLCPCB (part C2071517). 1 open-source board in 1 repository on GitHub use it.
Symbol
Footprint
From the datasheet
14- Supply, least
- 3.8 V · VIN, recommended operating min · p. 5
- Supply, most
- 40 V · VIN, recommended operating max · p. 5
- Supply, absolute maximum
- 42 V · VIN, absolute max DC · p. 5
- Works from
- -40 °C · Operating ambient temperature min · p. 5
- Works up to
- 85 °C · Operating ambient temperature max · p. 5
- Junction, hottest
- 160 °C · Junction temperature absolute max · p. 5
- Takes working
- 25 µA · VIN quiescent current typical, VEN floating, VFB = 1.0V · p. 6
- Takes asleep
- 1 µA · Shutdown supply current typical, VEN = 0V · p. 6
- Gives
- 5 A · Continuous output current max · p. 1
- Current limit
- 8 A · High-side peak current limit typical · p. 6
- Feedback reference
- 800 mV · Feedback voltage typical, CCM · p. 6
- Switches at
- 570 kHz · Oscillator frequency typical · p. 6
- Junction to air (SO-8EP)
- 45 K/W · Junction to ambient, four-layer FR-4 PCB, 2oz copper · p. 5
- Junction to case (SO-8EP)
- 5 K/W · Junction to case · p. 5
What it is and has
11- Converter
- 5A synchronous buck, 3.8V to 40V input · p. 11
- Package
- SO-8EP · p. 1
- Reference accuracy
- 0.8V ± 1% · p. 1
- Soft-start
- Programmable · p. 1
- EMI reduction
- Proprietary gate driver · p. 1
- Frequency spread spectrum
- Switching frequency jitter ±6% · p. 12
- Low-dropout operation
- LDO mode · p. 1
- Protection
- Undervoltage lockout · p. 1
- Protection
- Output overvoltage protection · p. 1
- Protection
- Cycle-by-cycle peak current limit · p. 1
- Protection
- Thermal shutdown · p. 1
Around it
14- cap 100nF
- between BST and SW; Ceramic bootstrap capacitor required for proper operation. · p. 16
- cap greater than 10µF
- between VIN and GND; Ceramic input capacitor sufficient for most applications; use low ESR. · p. 15
- cap 22µF to 68µF
- between VOUT and GND; Ceramic output capacitor with low ESR; verify transient and stability requirements. · p. 16
- cap at least 10nF
- between SS and GND; Soft-start capacitor; minimum soft-start time is 4ms. · p. 14
- cap 10pF to 220pF
- between VOUT and FB; Optional C4 to improve transient response. · p. 14
- ind approximately 1µH to 10µH
- between SW and VOUT; DC current rating at least 35% above maximum load current; DC resistance below 10mΩ for highest efficiency. · p. 15
- res 115.8 kΩ
- between VOUT and FB; R1 for the recommended 5.0V output configuration. · p. 14
- res 22.1 kΩ
- between FB and GND; R2 for the recommended 5.0V output configuration. · p. 14
- ind 3.6 µH
- between SW and VOUT; L for the recommended 5.0V output configuration. · p. 14
- cap 10 µF
- between VIN and GND; C1 for the recommended 5.0V output configuration. · p. 14
- cap 3 x 22 µF
- between VOUT and GND; C2 for the recommended 5.0V output configuration. · p. 14
- res 15.80 kΩ
- between COMP and C5; R5 in the series compensation network to GND for the recommended 5.0V output configuration. · p. 14
- cap 2.7 nF
- between R5 and GND; C5 in the series compensation network for the recommended 5.0V output configuration. · p. 14
- cap 33 pF
- between COMP and GND; Optional C6 for the recommended 5.0V output configuration. · p. 14
Specifications
39| Parameter | Conditions | As printed | Page |
|---|---|---|---|
| Supply Pin Voltage VIN | TA = +25°C; DC | min -0.3 · max 42 V | 5 |
| Supply Pin Voltage VIN | TA = +25°C; 400ms | min -0.3 · max 45 V | 5 |
| Enable/UVLO Pin Voltage VEN | TA = +25°C | min -0.3 · max 42 V | 5 |
| Soft-Start Pin Voltage VSS | TA = +25°C | min -0.3 · max 6 V | 5 |
| Feedback Pin Voltage VFB | TA = +25°C | min -0.3 · max 6 V | 5 |
| Compensation Pin Voltage VCOMP | TA = +25°C | min -0.3 · max 6 V | 5 |
| Switch Pin Voltage VSW | TA = +25°C; DC; upper limit VIN + 0.3 V | min -0.3 V | 5 |
| Switch Pin Voltage VSW | TA = +25°C; 20ns; upper limit VIN + 2.0 V | min -2.5 V | 5 |
| Storage Temperature TST | min -65 · max 150 °C | 5 | |
| Junction Temperature TJ | max 160 °C | 5 | |
| Lead Temperature TL | max 260 °C | 5 | |
| Human Body Model HBM | Note 5 | max 2000 V | 5 |
| Charged Device Model CDM | Note 5 | max 500 V | 5 |
| Junction to Ambient θJA | SO-8EP; FR-4 substrate, four-layer PC board, 2oz copper, minimum recommended pad layout | typ 45 °C/W | 5 |
| Junction to Case θJC | SO-8EP; FR-4 substrate, four-layer PC board, 2oz copper, minimum recommended pad layout | typ 5 °C/W | 5 |
| Supply Voltage VIN | TA = +25°C | min 3.8 · max 40 V | 5 |
| Output Voltage VOUT | TA = +25°C | min 0.8 · max 39 V | 5 |
| Operating Ambient Temperature Range TA | min -40 · max 85 °C | 5 | |
| Operating Junction Temperature Range TJ | min -40 · max 125 °C | 5 | |
| Shutdown Supply Current ISHDN | TA = +25°C, VIN = 12V; VEN = 0V | typ 1 · max 3 uA | 6 |
| Quiescent Supply Current IQ | TA = +25°C, VIN = 12V; VEN = Floating, VFB = 1.0V | typ 25 uA | 6 |
| VIN Undervoltage Rising Threshold UVLO | TA = +25°C, VIN = 12V unless otherwise specified | typ 3.5 · max 3.7 V | 6 |
| VIN Undervoltage Hysteresis UVLO | TA = +25°C, VIN = 12V unless otherwise specified | typ 400 mV | 6 |
| High-Side Power MOSFET On-Resistance (Note 8) RDS(ON)1 | TA = +25°C, VIN = 12V | typ 45 mΩ | 6 |
| Low-Side Power MOSFET On-Resistance (Note 8) RDS(ON)2 | TA = +25°C, VIN = 12V | typ 20 mΩ | 6 |
| HS Peak Current Limit (Note 8) IPEAK_LIMIT | TA = +25°C, VIN = 12V | min 6.8 · typ 8 · max 9.2 A | 6 |
| LS Valley Current Limit (Note 8) IVALLEY_LIMIT | TA = +25°C, VIN = 12V | typ 9 A | 6 |
| PFM Peak Current Limit IPFMPK | TA = +25°C, VIN = 12V | typ 950 mA | 6 |
| Zero Cross Current Threshold IZC | TA = +25°C, VIN = 12V | typ 0 mA | 6 |
| Oscillator Frequency fSW | TA = +25°C, VIN = 12V | min 510 · typ 570 · max 630 kHz | 6 |
| Minimum On-Time tON_MIN | TA = +25°C, VIN = 12V | typ 100 ns | 6 |
| Feedback Voltage VFB | TA = +25°C, VIN = 12V; CCM | min 792 · typ 800 · max 808 mV | 6 |
| EN Logic High Threshold VEN_H | TA = +25°C, VIN = 12V | typ 1.18 · max 1.25 V | 6 |
| EN Logic Low Threshold VEN_L | TA = +25°C, VIN = 12V | min 1.03 · typ 1.09 V | 6 |
| EN Input Current IEN | TA = +25°C, VIN = 12V; VEN = 1.5V | typ 5.5 uA | 6 |
| EN Input Current IEN | TA = +25°C, VIN = 12V; VEN = 1V | min 1 · typ 1.5 · max 2 uA | 6 |
| Soft-Start Time tSS | TA = +25°C, VIN = 12V; CSS = 10nF | typ 4 ms | 6 |
| Thermal Shutdown (Note 8) TSD | VIN = 12V | typ 160 °C | 6 |
| Thermal Shutdown Hysteresis (Note 8) THys | VIN = 12V | typ 25 °C | 6 |
Pins, by the datasheet
9- 1 BST
- High-side gate drive boost input; connect a 100nF capacitor from BST to SW. · p. 3
- 2 VIN
- Power input for the IC and converter MOSFETs; drive with 3.8V to 40V and bypass to GND. · p. 3
- 3 EN
- Enable and programmable UVLO input; high enables, low disables; connect to VIN or leave floating for automatic startup. · p. 3
- 4 SS
- Connect a ceramic capacitor to ground to program soft-start time; an internal 4uA source pulls SS toward VCC. · p. 3
- 5 FB
- Output voltage feedback input; connect to the output resistive divider. · p. 3
- 6 COMP
- Connect an external RC network to adjust loop response. · p. 3
- 7 GND
- Power ground. · p. 3
- 8 SW
- Power switching output; connect the output LC filter from SW to the output load. · p. 3
- 9 EXPOSED PAD
- Die heat dissipation path; must connect electrically to GND and the PCB ground plane. · p. 1
Open-source boards using it
1- 2 layers139 × 58.5 mm

Questions
Is there a KiCad symbol and footprint for the AP64501SP?
Yes. The symbol is EasyEDA_Cloud:AP64351SP-13 and the footprint EasyEDA_Cloud:SOIC-8_L4.9-W3.9-P1.27-LS6.0-BL-EP-1, both drawn on this page. PCBKit places them on a board for you when you design with it.
What package is the AP64501SP?
SOIC-8-EP, with 9 pins. Its footprint is drawn on this page.
Where is the AP64501SP datasheet?
Diodes Incorporated publishes it: the Datasheet link on this page opens it.
Where can I order the AP64501SP?
JLCPCB lists it as part C2071517, with 1 in stock; the sellers' links on this page open their listings.
Which open-source boards use the AP64501SP?
1 board in 1 repository on GitHub; the most starred are listed on this page, with their KiCad files.