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A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16B1B2B3B4B5B6B7B8B9B10B11B12B13B14B15B16C1C2C3C4C5C6C7C8C9C10C11C12C13C14C15C16D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15D16E1E2E3E4E5E6E7E8E9E10E11E12E13E14E15E16F1F2F3F4F5F6F7F8F9F10F11F12F13F14F15F16G1G2G3G4G5G6G7G8G9G10G11G12G13G14G15G16H1H2H3H4H5H6H7H8H9H10H11H12H13H14H15H16J1J2J3J4J5J6J7J8J9J10J11J12J13J14J15J16K1K2K3K4K5K6K7K8K9K10K11K12K13K14K15K16L1L2L3L4L5L6L7L8L9L10L11L12L13L14L15L16M1M2M3M4M5M6M7M8M9M10M11M12M13M14M15M16N1N2N3N4N5N6N7N8N9N10N11N12N13N14N15N16P1P2P3P4P5P6P7P8P9P10P11P12P13P14P15P16R1R2R3R4R5R6R7R8R9R10R11R12R13R14R15R16T1T2T3T4T5T6T7T8T9T10T11T12T13T14T15T16

EP4CE6F17C8

ALTERA

Cyclone IV E Family, FPGA, 6272 LEs, 179 I/Os, 256-Pin FBGA, Commercial Grade, Speed Grade 8

Part id
altera/EP4CE6F17C8
Category
Uncategorised
Package
BGA256
Pins
256
Used on
1 open-source board

Overview

The EP4CE6F17C8 is an uncategorised made by ALTERA in a BGA256 package with 256 pins. Cyclone IV E Family, FPGA, 6272 LEs, 179 I/Os, 256-Pin FBGA, Commercial Grade, Speed Grade 8.

PCBKit's library has its KiCad symbol (Logic:EP4CE6F17C8, from CERN's library) and its footprint (ICs And Semiconductors SMD_BGA:BGA256C100P16X16_1700X1700X155, from CERN's library), ready for a KiCad board. 1 open-source board in 1 repository on GitHub use it.

Symbol

D4IOE5IOF5IOB1IO,_(DQS2L/CQ3L)/(DQS2L/CQ3L)C2IO,_DIFFIO_L1pC1IO,_DIFFIO_L1n,_(DATA1,ASDO)F3IO,_VREFB1N0D2IO,_DIFFIO_L2p,_(FLASH_nCE,nCSO)D1IO,_DIFFIO_L2nG5IOF2IO,_DIFFIO_L3pF1IO,_DIFFIO_L3nG2IO,_DIFFIO_L4p,_(DQS0L/CQ1L,DPCLK0)/(DQS0L/CQ1L,DPCLK0)G1IO,_DIFFIO_L4nH2IO,_(DATA0)
Logic:EP4CE6F17C8From CERN's library

Footprint

A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16B1B2B3B4B5B6B7B8B9B10B11B12B13B14B15B16C1C2C3C4C5C6C7C8C9C10C11C12C13C14C15C16D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15D16E1E2E3E4E5E6E7E8E9E10E11E12E13E14E15E16F1F2F3F4F5F6F7F8F9F10F11F12F13F14F15F16G1G2G3G4G5G6G7G8G9G10G11G12G13G14G15G16H1H2H3H4H5H6H7H8H9H10H11H12H13H14H15H16J1J2J3J4J5J6J7J8J9J10J11J12J13J14J15J16K1K2K3K4K5K6K7K8K9K10K11K12K13K14K15K16L1L2L3L4L5L6L7L8L9L10L11L12L13L14L15L16M1M2M3M4M5M6M7M8M9M10M11M12M13M14M15M16N1N2N3N4N5N6N7N8N9N10N11N12N13N14N15N16P1P2P3P4P5P6P7P8P9P10P11P12P13P14P15P16R1R2R3R4R5R6R7R8R9R10R11R12R13R14R15R16T1T2T3T4T5T6T7T8T9T10T11T12T13T14T15T16
ICs And Semiconductors SMD_BGA:BGA256C100P16X16_1700X1700X155From CERN's library

Pinout

256
The pins of the EP4CE6F17C8
PinNameType
A1VCCIO8Power in
A2IO,_DIFFIO_T5nInput/output
A3IO,_DIFFIO_T2nInput/output
A4IO,_DIFFIO_T4n,_(DM3T/BWS#3T)/(DM5T/BWS#5T)Input/output
A5IO,_DIFFIO_T6n,_(DATA7),_(DQ3T)/(DQ5T)Input/output
A6IO,_DIFFIO_T7n,_(DQS3T/CQ3T#)/(DQS3T/CQ3T#)Input/output
A7IO,_DIFFIO_T9n,_(DQ3T)/(DQ5T)Input/output
A8IO,_DIFFIO_T11nInput/output
A9IO,_DIFFIO_T12nInput/output
A10IO,_DIFFIO_T14n,_(DQ5T)/(DQ5T)Input/output
A11IO,_DIFFIO_T17n,_(DQ5T)/(DQ5T)Input/output
A12IO,_DIFFIO_T18n,_(DQ5T)/(DQ5T)Input/output
A13IO,_DIFFIO_T19nInput/output
A14IO,_PLL2_CLKOUTnInput/output
A15IO,_DIFFIO_T15pInput/output
A16VCCIO7Power in
B1IO,_(DQS2L/CQ3L)/(DQS2L/CQ3L)Input/output
B2GNDPower in
B3IO,_DIFFIO_T2p,_(DQS1T/CQ1T#,DPCLK7)/(DQS1T/CQ1T#,DPCLK7)Input/output
B4IO,_DIFFIO_T4pInput/output
B5IO,_DIFFIO_T5p,_(DQ3T)/(DQ5T)Input/output
B6IO,_DIFFIO_T7p,_(DQ3T)/(DQ5T)Input/output
B7IO,_DIFFIO_T9p,_(DATA4),_(DQ3T)/(DQ5T)Input/output
B8IO,_DIFFIO_T11pInput/output
B9IO,_DIFFIO_T12pInput/output
B10IO,_DIFFIO_T14p,_(DQ5T)/(DQ5T)Input/output
B11IO,_DIFFIO_T17p,_(DQ5T)/(DQ5T)Input/output
B12IO,_DIFFIO_T18p,_(DQ5T)/(DQ5T)Input/output
B13IO,_DIFFIO_T19p,_(DQ5T)/(DQ5T)Input/output
B14IO,_PLL2_CLKOUTpInput/output
B15GNDPower in
B16IO,_(DQS0R/CQ1R,DPCLK5)/(DQS0R/CQ1R,DPCLK5)Input/output
C1IO,_DIFFIO_L1n,_(DATA1,ASDO)Input/output
C2IO,_DIFFIO_L1pInput/output
C3IO,_DIFFIO_T1nInput/output
C4VCCIO8Power in
C5GNDPower in
C6IO,_VREFB8N0Input/output
C7VCCIO8Power in
C8IO,_(DQS5T/CQ5T#)/(DQS5T/CQ5T#)Input/output
C9IO,_DIFFIO_T13n,_(DQ5T)/(DQ5T)Input/output
C10VCCIO7Power in
C11IO,_VREFB7N0Input/output
C12GNDPower in
C13VCCIO7Power in
C14IO,_DIFFIO_T21nInput/output
C15IO,_DIFFIO_R1pInput/output
C16IO,_DIFFIO_R1n,_(DQS2R/CQ3R)/(DQS2R/CQ3R)Input/output
D1IO,_DIFFIO_L2nInput/output
D2IO,_DIFFIO_L2p,_(FLASH_nCE,nCSO)Input/output
D3IO,_DIFFIO_T1pInput/output
D4IOInput/output
D5IO,_DIFFIO_T3nInput/output
D6IO,_DIFFIO_T3pInput/output
D7GNDPower in
D8IO,_(DQ3T)/(DQ5T)Input/output
D9IO,_DIFFIO_T13p,_(DM5T/BWS#5T)/(DM5T/BWS#5T)Input/output
D10GNDPower in
D11IO,_DIFFIO_T20nInput/output
D12IO,_DIFFIO_T20p,_(DQS0T/CQ1T,DPCLK6)/(DQS0T/CQ1T,DPCLK6)Input/output
D13VCCD_PLL2Power in
D14IO,_DIFFIO_T21p,_(DQ5T)/(DQ5T)Input/output
D15IO,_DIFFIO_R2pInput/output
D16IO,_DIFFIO_R2nInput/output
E1CLK1,_DIFFCLK_0nInput
E2GNDPower in
E3VCCIO1Power in
E4GNDPower in
E5IOInput/output
E6IO,_(DATA6),_(DQ3T)/(DQ5T)Input/output
E7IO,_(DATA5),_(DQ3T)/(DQ5T)Input/output
E8IO,_DIFFIO_T10n,_(DATA2),_(DQ3T)/(DQ5T)Input/output
E9IO,_(DQS4T/CQ5T)/(DQS4T/CQ5T)Input/output
E10IO,_RDN4Input/output
E11IO,_RUP4Input/output
E12GNDA2Power in
E13GNDPower in
E14VCCIO6Power in
E15CLK4,_DIFFCLK_2pInput
E16CLK5,_DIFFCLK_2nInput
F1IO,_DIFFIO_L3nInput/output
F2IO,_DIFFIO_L3pInput/output
F3IO,_VREFB1N0Input/output
F4nSTATUSInput/output
F5IOInput/output
F6IO,_DIFFIO_T8nInput/output
F7IO,_DIFFIO_T8pInput/output
F8IO,_DIFFIO_T10p,_(DATA3)Input/output
F9IO,_DIFFIO_T16p,_(DQS2T/CQ3T)/(DQS2T/CQ3T)Input/output
F10IO,_DIFFIO_T16nInput/output
F11IO,_DIFFIO_T15nInput/output
F12VCCA2Power in
F13IOInput/output
F14IO,_VREFB6N0Input/output
F15IO,_DIFFIO_R3p,_(CLKUSR)Input/output
F16IO,_DIFFIO_R3n,_(nCEO)Input/output
G1IO,_DIFFIO_L4nInput/output
G2IO,_DIFFIO_L4p,_(DQS0L/CQ1L,DPCLK0)/(DQS0L/CQ1L,DPCLK0)Input/output
G3VCCIO1Power in
G4GNDPower in
G5IOInput/output
G6VCCINTPower in
G7VCCINTPower in
G8VCCINTPower in
G9VCCINTPower in
G10VCCINTPower in
G11IOInput/output
G12MSEL2Input
G13GNDPower in
G14VCCIO6Power in
G15IO,_DIFFIO_R4p,_(CRC_ERROR)Input/output
G16IO,_DIFFIO_R4n,_(INIT_DONE)Input/output
H1DCLKInput/output
H2IO,_(DATA0)Input/output
H3TCKInput
H4TDIInput
H5nCONFIGInput
H6VCCINTPower in
H7GNDPower in
H8GNDPower in
H9GNDPower in
H10GNDPower in
H11VCCINTPower in
H12MSEL1Input
H13MSEL0Input
H14CONF_DONEInput/output
H15GNDPower in
H16GNDPower in
J1IO,_DIFFIO_L5n,_(DQ1L)Input/output
J2IO,_DIFFIO_L5p,_(DQ1L)Input/output
J3nCEInput
J4TDOOutput
J5TMSInput
J6IOInput/output
J7GNDPower in
J8GNDPower in
J9GNDPower in
J10GNDPower in
J11IOInput/output
J12IO,_DIFFIO_R6pInput/output
J13IO,_(DQ1R)Input/output
J14IO,_DIFFIO_R6n,_(DQ1R)Input/output
J15IO,_DIFFIO_R7p,_(DEV_CLRn)Input/output
J16IO,_DIFFIO_R7n,_(DEV_OE)Input/output
K1IO,_DIFFIO_L7n,_(DQ1L)Input/output
K2IO,_DIFFIO_L7pInput/output
K3VCCIO2Power in
K4GNDPower in
K5IO,_RUP1,_(DQ1L)Input/output
K6IO,_DIFFIO_L6pInput/output
K7VCCINTPower in
K8IO,_DIFFIO_B5nInput/output
K9IO,_DIFFIO_B13pInput/output
K10IO,_DIFFIO_B18pInput/output
K11IOInput/output
K12IOInput/output
K13GNDPower in
K14VCCIO5Power in
K15IO,_DIFFIO_R8p,_(DQS1R/CQ1R#,DPCLK4)/(DQS1R/CQ1R#,DPCLK4)Input/output
K16IO,_DIFFIO_R8n,_(DQ1R)Input/output
L1IO,_DIFFIO_L8n,_(DQ1L)Input/output
L2IO,_DIFFIO_L8p,_(DQS1L/CQ1L#,DPCLK1)/(DQS1L/CQ1L#,DPCLK1)Input/output
L3IO,_VREFB2N0Input/output
L4IO,_RDN1,_(DQ1L)Input/output
L5VCCA1Power in
L6IO,_DIFFIO_L6nInput/output
L7IO,_(DQ3B)/(DQ5B)Input/output
L8IO,_DIFFIO_B9p,_(DQ3B)/(DQ5B)Input/output
L9IO,_DIFFIO_B13nInput/output
L10IO,_DIFFIO_B18nInput/output
L11IO,_DIFFIO_B21nInput/output
L12IOInput/output
L13IO,_(DQ1R)Input/output
L14IO,_VREFB5N0Input/output
L15IO,_DIFFIO_R9pInput/output
L16IO,_DIFFIO_R9n,_(DQ1R)Input/output
M1CLK3,_DIFFCLK_1nInput
M2CLK2,_DIFFCLK_1pInput
M3VCCIO2Power in
M4GNDPower in
M5GNDA1Power in
M6IO,_(DQ3B)/(DQ5B)Input/output
M7IO,_DIFFIO_B5p,_(DQS3B/CQ3B#)/(DQS3B/CQ3B#)Input/output
M8IO,_DIFFIO_B9n,_(DM5B/BWS#5B)/(DM5B/BWS#5B)Input/output
M9IO,_DIFFIO_B14pInput/output
M10IO,_RUP2Input/output
M11IO,_DIFFIO_B22pInput/output
M12IOInput/output
M13GNDPower in
M14VCCIO5Power in
M15CLK6,_DIFFCLK_3pInput
M16CLK7,_DIFFCLK_3nInput
N1IO,_DIFFIO_L9n,_(DQ1L)Input/output
N2IO,_DIFFIO_L9p,_(DQ1L)Input/output
N3IO,_DIFFIO_B1pInput/output
N4VCCD_PLL1Power in
N5IO,_DIFFIO_B4p,_(DQ3B)/(DQ5B)Input/output
N6IO,_DIFFIO_B4n,_(DQ3B)/(DQ5B)Input/output
N7GNDPower in
N8IO,_DIFFIO_B10p,_(DQ5B)/(DQ5B)Input/output
N9IO,_DIFFIO_B14n,_(DQ5B)/(DQ5B)Input/output
N10GNDPower in
N11IO,_RDN2Input/output
N12IO,_DIFFIO_B22nInput/output
N13IOInput/output
N14IO,_RUP3,_(DM1R/BWS#1R)Input/output
N15IO,_DIFFIO_R10p,_(DQ1R)Input/output
N16IO,_DIFFIO_R10n,_(DQ1R)Input/output
P1IO,_DIFFIO_L10n,_(DM1L/BWS#1L)Input/output
P2IO,_DIFFIO_L10p,_(DQ1L)Input/output
P3IO,_DIFFIO_B1n,_(DM3B/BWS#3B)/(DM5B/BWS#5B)Input/output
P4VCCIO3Power in
P5GNDPower in
P6IO,_VREFB3N0Input/output
P7VCCIO3Power in
P8IO,_DIFFIO_B10n,_(DQ5B)/(DQ5B)Input/output
P9IO,_(DQS2B/CQ3B)/(DQS2B/CQ3B)Input/output
P10VCCIO4Power in
P11IO,_VREFB4N0Input/output
P12GNDPower in
P13VCCIO4Power in
P14IO,_DIFFIO_B21pInput/output
P15IO,_RDN3,_(DQ1R)Input/output
P16IO,_DIFFIO_R11n,_(DQS3R/CQ3R#)/(DQS3R/CQ3R#)Input/output
R1IO,_(DQS3L/CQ3L#)/(DQS3L/CQ3L#)Input/output
R2GNDPower in
R3IO,_DIFFIO_B2p,_(DQ3B)/(DQ5B)Input/output
R4IO,_PLL1_CLKOUTpInput/output
R5IO,_DIFFIO_B6p,_(DQ3B)/(DQ5B)Input/output
R6IO,_DIFFIO_B7p,_(DQ3B)/(DQ5B)Input/output
R7IO,_DIFFIO_B8p,_(DQ3B)/(DQ5B)Input/output
R8IO,_DIFFIO_B11pInput/output
R9IO,_DIFFIO_B12pInput/output
R10IO,_DIFFIO_B15p,_(DQ5B)/(DQ5B)Input/output
R11IO,_DIFFIO_B16p,_(DQ5B)/(DQ5B)Input/output
R12IO,_DIFFIO_B17p,_(DQ5B)/(DQ5B)Input/output
R13IO,_DIFFIO_B19pInput/output
R14IOInput/output
R15GNDPower in
R16IO,_DIFFIO_R11p,_(DQ1R)Input/output
T1VCCIO3Power in
T2IO,_(DQS1B/CQ1B#,DPCLK2)/(DQS1B/CQ1B#,DPCLK2)Input/output
T3IO,_DIFFIO_B2nInput/output
T4IO,_PLL1_CLKOUTnInput/output
T5IO,_DIFFIO_B6nInput/output
T6IO,_DIFFIO_B7nInput/output
T7IO,_DIFFIO_B8n,_(DQS5B/CQ5B#)/(DQS5B/CQ5B#)Input/output
T8IO,_DIFFIO_B11nInput/output
T9IO,_DIFFIO_B12nInput/output
T10IO,_DIFFIO_B15n,_(DQS4B/CQ5B)/(DQS4B/CQ5B)Input/output
T11IO,_DIFFIO_B16nInput/output
T12IO,_DIFFIO_B17n,_(DQ5B)/(DQ5B)Input/output
T13IO,_DIFFIO_B19n,_(DQ5B)/(DQ5B)Input/output
T14IO,_DIFFIO_B20p,_(DQ5B)/(DQ5B)Input/output
T15IO,_DIFFIO_B20n,_(DQS0B/CQ1B,DPCLK3)/(DQS0B/CQ1B,DPCLK3)Input/output
T16VCCIO4Power in

Open-source boards using it

1
  • 4 layers63.2 × 47.8 mmJulia v2.1.1.0, the printed circuit board in 3D

    Julia v2.1.1.0

    iank/julia_lcd

    TFT LCD panel, capacitive touch controller, Xilinx Cyclone IV FPGA, SDR SDRAM

    104 parts3

Parts like it

8

Questions

Is there a KiCad symbol and footprint for the EP4CE6F17C8?

Yes. The symbol is Logic:EP4CE6F17C8 and the footprint ICs And Semiconductors SMD_BGA:BGA256C100P16X16_1700X1700X155, both drawn on this page. PCBKit places them on a board for you when you design with it.

What package is the EP4CE6F17C8?

BGA256, with 256 pins. Its footprint is drawn on this page.

What can replace the EP4CE6F17C8?

Parts like it in the library: the ADC12DL2500ACF by Texas Instruments, the 5M2210ZF256C5N by ALTERA, the EP2C8F256C6N by ALTERA and the 10M04DAF256C8G by INTEL. Check their datasheets: a part that fits the footprint may still differ in its ratings.

Which open-source boards use the EP4CE6F17C8?

1 board in 1 repository on GitHub; the most starred are listed on this page, with their KiCad files.