Echometer

Hardware — analog front end, power, PCB and acoustics

KiCad 10 project (v4.kicad_pro, schematic + 4-layer PCB), fabrication outputs in fab/, BOM in v4.csv, and the parametric acoustic-horn generator ultrasonic_horn_freecad.py.

The schematic is split over two sheets: v4.kicad_sch (root) and MCU.kicad_sch (everything — front end, ADC, power, module headers).

Read the errata in the top-level README before ordering. Item 1 is blocking: two of the three gain-select signals land on the octal-PSRAM bus and must be moved.

Analog front end

Transducer

Knowles SPU0410LR5H-QB, one fitted. An analog MEMS mic with usable response through the target bat band; its raw output is small — tens of millivolts for a loud, close call — so it must be amplified and biased into the ADC's input range before sampling.

The 0.25 mm acoustic port sits at the throat of the conical horn.

Op-amp choice

The amplifier must pass the full ultrasonic band and apply large gain without rolling off, which sets a hard requirement on gain–bandwidth product: GBW ≥ gain × 120 kHz. Two devices:

Both run single-supply and bias the signal to mid-rail (VREF ≈ 1.65 V) so the AC waveform swings symmetrically inside the ADC's 0–3.3 V window. A TI TPS74801 low-noise LDO supplies the analog rail and VREF, so digital switching noise doesn't couple into the µV-level mic signal.

Note the OPA838's decompensation: its minimum stable gain is +7, which is a real constraint on the gain-step table below — stage 1's low setting of 4.25 would be unstable on its own, and is only usable because C14 (27 pF across R13) provides the compensation the topology needs.

Gain — how the switching works

Both stages are non-inverting with a 1 kΩ leg to VREF. Each has a permanent feedback resistor, and a 74HC4053 analog mux switches further resistors in parallel with it, which lowers the gain.

Three design decisions are load-bearing here:

The permanent resistors are never switched out. The loop is closed in every mux state, including the ~300 ms before firmware runs and the instant the mux transitions. Nothing can rail.

The polarity is chosen so reset means quiet. The 4053 selects Y0 — resistor connected, parallel combination, lower gain — when its select pin is LOW. GPIOs sit low at reset, so the board wakes at minimum gain, which cannot clip.

The switches sit at the summing node, mux common to the op-amp inverting input and the resistors to Y0. Both sides of a closed switch are therefore at virtual ground, so the mux's on-resistance sees an almost constant voltage. That is what keeps the 4053's on-resistance nonlinearity out of the signal — put the switch anywhere the voltage swings and it becomes a distortion source.

Why the switches are split 1 / 2 across the stages. Switching resistors in parallel adds conductances, so the achievable ratio within one stage is bounded — a single stage can only span about 18 dB however you pick the values. Two stages multiply, giving the full 31 dB.

The six steps

Steps are 5.6–7.3 dB apart. "Clips near" is the input SPL at which the TL972 output hits its rail, for the SPU0410 at −38 dBV/Pa with ~1.45 V of peak swing.

Three switches give 8 states, not 6. The two omitted (177× and 26×) sit within 1.5 dB of a neighbour, and that bunching is unavoidable: the four states of two parallel switches always satisfy G(both) = G(a) + G(b) − G(neither), so they cannot be spaced evenly.

Input common-mode headroom — checked, and why VREF must stay mid-rail

Neither amp has a rail-to-rail input stage, and both stages are non-inverting, so the + input carries signal rather than sitting still. On a 3.3 V rail:

Both pass. The TL972's is the tighter one and it appears at the lowest gain step, where the output is clipping at ±1.45 V and its + input therefore has to swing ±279 mV. The OPA838 is never stressed because its + input only ever carries the mic-level signal, at most ±66 mV — the mic itself runs out (AOP ≈ 120 dB SPL) at about the same point its 2.0 V ceiling would be reached.

The useful consequence: the safe window is the intersection, 1.15 – 2.00 V, and VREF at 1.65 V sits near its centre. Do not "improve" headroom by moving VREF down — 1.15 V is a hard floor for the TL972, and anything below ~1.4 V starts eating the margin you gained at the top.

Why the gain stops at 782×

The SPU0410's own noise integrated over 20–120 kHz is around 38 dB SPL, and a bat at 30 m arrives at roughly 30 dB SPL. Past ~800× you are amplifying mic noise, not signal.

v3's jump from 121× to 625× helped because at 121× the ADC's LSB was still competing with the mic noise; at 782× the mic dominates and more gain buys nothing. Further range has to come from narrowband processing — FFT bin energy, matched filter — not from the front end.

Filtering — ultrasonic only

Two of these look similar and do opposite jobs, and v3 got one of them wrong. R18/C19 is a power-supply filter on the mic's VDD pin — it wants its corner far below the band, and 159 Hz gives about 48 dB of rejection at 40 kHz. v3 used 10 Ω + 110 nF, which corners at 159 kHz and therefore did essentially nothing. C12/C13 are the signal high-pass and want their corners at the band edge.

The anti-alias filter had the same class of bug in v3: 100 Ω + 10 nF corners at 159 kHz, above the 128 kHz Nyquist, so it wasn't anti-aliasing anything. 22 nF brings it to 72 kHz.

Keeping R6/R12 at 1 kΩ is what let both 27 pF compensation caps stay. Scaling the network up 10× for resistor accuracy would have demanded ~2 pF caps, which are not buildable against stray capacitance. Mux on-resistance instead adds 1.5 % error at the 33 k tap and 4 % at the 6k8 tap — irrelevant for a detector.

Digital acquisition

Sampling is done by an external 12-bit SAR ADC (ADCS7476, rated 1 MSPS) run at 256 ksps → 128 kHz Nyquist, covering the full bat band. The ESP32-S3's built-in ADC-DMA path tops out near 83 ksps — far too slow — so the external ADC is clocked with a hardware trick:

• The I²S peripheral runs as master, 16-bit stereo, so its WS line toggles every 16 bit-clocks.
• WS → ADC CS, BCK → SCLK, SDATA → I²S DIN. WS-low frames each conversion (16 clocks readout); WS-high is the re-track gap.
• I²S RX DMA captures every sample jitter-free with zero per-sample CPU. At 256 ksps the bit clock is 256000 × 2 × 16 = 8.192 MHz.

Buffers of 2048 samples (one FFT frame, 8 ms) feed the detector — 125 Hz/bin resolution; the detection band starts at bin 152 (19 kHz). See ../firmware/README.md for the detection logic and the bit-alignment quirk in the returned word.

The ADC input is driven from the TL972 output through R17 (100 Ω), so unlike v3 it can never float. A floating ADC input is an antenna, and touching it false-triggered v3's detector every time.

Signal levels & detection budget

The FFT detection threshold (ULTRASONIC_THRESH_COUNTS) sits a few dB above the amplified noise floor. Because the gain is now variable, that fixed count threshold represents a different absolute sensitivity at each step — see the roadmap note about an adaptive trigger.

Power

USB ──▶ TP4056 ──▶ [cell] ──▶ DW01/FS8205 ──▶ Lipo+ ─┬─▶ MT3608 ──▶ +5V ──▶ ESP32 module
                                                     │              └──▶ TPS74801 BIAS
                                                     └──────────────────▶ TPS74801 IN ──▶ +3V3 analog

The LDO is fed from the battery, not from the boost

That is the whole point of the TPS74801's separate BIAS pin. BIAS runs the control loop and the gate driver, so the pass FET can be driven above VIN. That lets IN sit at the raw cell voltage (3.0–4.2 V) and drop only ~50 mV at the ~25 mA the analog side draws.

The win isn't efficiency — it's noise. Routed the obvious way (LDO fed from the boost output), the analog rail inherits the MT3608's 1.2 MHz switching ripple, and no LDO's PSRR is good at 1.2 MHz. Feeding it from the cell means the analog rail never sees the switcher at all.

Boost output is 5.31 V, not 5.0 V, and that is deliberate. BIAS must stay at least 1.62 V above the 3.3 V output, i.e. ≥ 4.92 V. At 5.1 V there was only 180 mV of margin — about what a Wi-Fi TX burst eats. Measure the sag on a real board; if +5 V dips below 4.92 V during TX, the LDO loses bias headroom and the analog rail glitches during exactly the moments you transmit.

Charging and switching, both with caveats

Charging while running works — the cell buffers everything — but the load current means the TP4056 may never see its termination threshold. It can sit in CV at 4.2 V indefinitely and the green LED may never come on. Don't leave it plugged in for days.

There is no power switch. The boost's EN is tied to its own input, so the board runs from the moment the cell is connected; unplug J6 to stop it. Standby drain as built is 50–120 mA, which flattens 2000 mAh in 17–40 hours and then parks the cell at the DW01's 2.4 V cutoff — bad for storage.

If you add a switch, put it in the Lipo+ → L1 / U8.5 branch, not on the boost's EN pin. The MT3608 is asynchronous, so Lipo+ → L1 → D3 → +5V is a permanent DC path: disabling the boost leaves the module's regulator powered anyway. Breaking the boost input kills that path and still leaves the charger connected.

Pinout — ESP32-S3 DevKitC-1

The SD lines are wired but unused by the current firmware; J5 must be an SD module with its own regulator and level shifters, since it is fed +5 V on pin 5 and the SPI lines are unbuffered.

Acoustics — the conical horn

ultrasonic_horn_freecad.py is a parametric generator for a conical horn that concentrates incoming ultrasound onto the mic port. It is free SNR, ahead of the electronics.

At 108 kHz the 28 mm mouth is ~8.8 wavelengths across — well above cutoff, so the horn still delivers strong on-axis gain, just with a narrower beam that must be aimed more precisely.

Bat call levels, directivity and detection range

Engineering estimates for sizing the front end — not species-accurate field data.

Source levels

Cross-reference this against the "clips near" column in the gain table: a loud hawker at a few metres wants the 22× or 51× step, while a distant pass wants 782×. That 31 dB spread is exactly the range v3's single fixed 625× could not cover.

Target species — least horseshoe bat (Rhinolophus pusillus)

Consequences for the design:

• A fast external ADC is mandatory. At 108 kHz the call needs > 216 ksps; an MCU's internal ADC at 83 ksps could not see this species at all, and even v2's 240 ksps left it at the very edge of the band. Hence the ADCS7476 at 256 ksps.
• The narrowband CF tone is the easy case for the FFT detector — its energy piles into one bin. Narrowing the detection window to ~100–115 kHz (bins ~800–920) would target this species specifically and reject the ~50 kHz USB noise interferer entirely.

Directivity

Estimated detection range

Loud bat, SL = 110 dB SPL @ 1 m on-axis; minimum detectable ≈ 40 dB SPL:

Optimistic ceilings — quiet bats, off-axis calls, and weather cut these substantially.

Bill of materials

Full BOM in v4.csv, regenerated from the schematic with kicad-cli sch export bom. The parts that define the design:

Known BOM issue: several passive symbols still carry the Part# and LCSC Part # of their previous value — R13, R23/R25, R24 and R26 inherit a 24 kΩ part number, and C16 inherits a 10 nF one. Those fields are cleared in the checked-in v4.csv, so ordering from it is safe, but fix the symbol properties before the next export.

altium_ascii_to_kicad.py is a helper for importing Altium ASCII footprints into the KiCad library; it is not part of the build.