Bionic base

Contents

• CPUs — every target supported and planned, with the variants each detects
• Hardware — the board stack, signal naming and the awkward chips
• 3.3 V base — planned second base board, its keying and what it unlocks
• Debugger — full command reference
• Build & run — toolchain, flashing, serial ports
• Samples — the programs and how to run them
• CPU speed by an assembly-language Mandelbrot — the benchmark's seconds per frame on each chip
• Demos — recorded terminal sessions, and what to watch for in them

What is this?

Put a real MC6809, Z80, TMS9900 or CDP1802 into a ZIF socket and single-step it, one bus cycle at a time, from a terminal on your desk.

Bionic runs genuine vintage processors — not emulations of them. A Teensy 4.1 is wired to every pin of the target CPU and drives the whole system around it: the clock, every bus cycle, and the memory and peripherals the chip thinks it is talking to. One firmware image — about 470 kB including every assembler, disassembler and debugger — covers all 50 supported targets, and the board tells the controller which one it is.

The hardware is two boards:

1. Base — the Teensy 4.1, five TXS0108E level shifters for 3.3 V ↔ 5 V translation, data bus holders, the 48-pin ZIF socket and the HALT/RUN switch.
2. CPU adapter — one small board per processor, holding little more than the chip itself, its identity EEPROM and whatever power the part demands. The TMS9900 board, for example, generates its own +12 V and −5 V rails and a non-overlapping four-phase clock, and CPUs with large address spaces carry an address bus multiplexer.

The 48 signals crossing the connector are named P10–P57, and each CPU board maps them to its own pinout in a small TOML file. See docs/hardware.md.

Debugger features

• Single-step a physical CPU and print every bus cycle it performed (S).
• Live disassembly of the next instruction after each register dump, via libasm.
• Registers read back by injecting instructions and capturing the resulting cycles — read and write them (r, =).
• Breakpoints, up to 4 plus one temporary for run-until-address (B, b, g).
• Memory dump and patch, separate program and data spaces for Harvard architectures (d, p, m, M), plus a write-protect area on targets that need one (P).
• Upload Intel HEX or Motorola S-record straight over the serial link (U).
• Emulated peripherals — MC6850 ACIA and i8251 USART — and on-chip serial ports of MCU targets bridged to your terminal (I).
• Automatic board identification from a UNI/O serial EEPROM, plus runtime variant detection: one 6502 board reports MOS6502, G65SC02, R65C02, W65C02S or W65C816S depending on which die actually responds.

Supported CPUs

All 50 targets, grouped by vendor and architecture:

Targets in italics are variants the firmware identifies at runtime, by executing instructions that behave differently on each die — not by anything written on the board.

See docs/supported-cpus.md for the full table, including the CPUs still to be supported.

Repository layout

Related projects

Resources

• Recorded sessions — asciinema.org/~tgtakaoka
• Progress log — Bluesky · X

License

Licensed under the Apache License, Version 2.0.