QuadCom 8b

Wrap030

An ever-evolving homebrew 68030 computer.

Wrap030 got its name from its beginnings. It started as a wire-wrapped single board computer built largely from parts on-hand and what could be acquired locally. It was incredibly unstable.

Since then, it has gone through several major stages, adding new hardware and updating its memory map along the way. It currently exists as a stack of PCBs with a three ribbon cable main bus linking them. Many odd decisions and design constraints carry forward from that initial wire-wrap prototype.

The primary goal of the project is to learn how to build a 32-bit computer from the ground up, and at that it has been incredibly successful. A secondary long-term goal was to build something capable of running a Unix-like operating system, and has had some success there as well.

A rough log of development is tagged wrap030 on techav.net.

Software

Bootloader

ROM bootloader will read & execute BOOT.BIN from a FAT16-formatted CompactFlash card.

MultiBASIC

MultiBASIC is a minimal just-enough-OS kernel for running 8 simultaneous instances of EhBASIC. It uses the 68030 MMU to implement memory protection and supports pre-emptive multitasking.

NetBSD

In early 2025, the project had finally reached a state where it was stable enough and had all of the critical hardware components to try to port a proper operating system. NetBSD was chosen because of its active m68k development and relative ease of understanding. One month was devoted to attempting to port NetBSD to Wrap030 with the result being a functional single-user root shell. Full multi-user booting was not successful. The results of that work are in a separate repo, netbsd-wrap030.

Hardware

Memory Map

Startup Overlay

On reset, ROM is overlaid on top of RAM at address 0x00000000. All reads from the lowest 512k addresses will be passed to ROM instead of RAM. Writes are passed through to RAM.

Writing 0 to the overlay register will disable the startup overlay. Attempting to write to the overlay port again should not be attempted.

IDE Controller

The IDE controller is little more than some buffers on the main bus, with a little glue logic for timing. Data bytes are swapped in hardware. This means byte commands can be sent to the interface unmodified, but 16-bit read/write data needs to be swapped in software.

Custom Interval Timer

The interval timer is a minimal custom design implemented using spare macrocells in the DRAM controller CPLD. Writing to the timer register will start the timer count. It will continue counting until it reaches 0, where it will hold until the count register is written to again. Timer interrupt request is asserted when the count reaches 1 and remains asserted until the count register is written to again. Writing 0 to the count register will disable the timer.

Since the timer is part of the DRAM control logic, it latches the least-significant 16 address bits as the count value. The value on the data bus is ignored.

The countdown runs at main bus frequency, 25MHz, so a count of 25,000 would be roughly a 1ms interval (plus interrupt servicing overhead). The maximum count is 65,535, which would be a little over 2.5ms.