IRIS-868

⚡ At a glance

[!WARNING] Revision B is design-complete but has not been bring-up tested. Fabrication files are released as-is. No firmware is included in this repository yet.

📑 Table of contents

• What's new in revision B
• Gallery
• System architecture
• Repository layout
• Hardware overview
• Pin assignment
• Board specification
• Bill of materials
• Getting started
• Releases

🆕 What's new in revision B

A design review before release added these changes:

• RF feed: the antenna trace no longer runs under the module, and J6 moved to suit (see RF chain).
• Decoupling: C10 now sits next to the NRST pin, and C8 next to the VDDA pin.
• Clean-up: the unused test pad under IC1 was removed.
• Fabrication: design constraints follow JLCPCB's limits, with a green mask so the solder dams between LQFP pins can be kept.

🖼️ Gallery

Front	Back

📄 Full schematic: docs/schematics/IRIS-868.pdf

🏗️ System architecture

flowchart LR
    USB["USB micro-B<br/>J2"] -->|VBUS 5 V| LDO["AP2112K-3.3<br/>600 mA LDO"]
    USB -.->|"D+ / D-"| ESD["USBLC6-2SC6<br/>ESD"]
    ESD -.-> MCU
    USB -->|"VBUS ÷ 4.13"| VMON["V_MON<br/>PC0 / ADC"]
    VMON --> MCU

    LDO --> RAIL(("3.3 V"))
    RAIL -->|"FB1 120 Ω"| VDDA["+3.3VA"]
    RAIL -->|"FB2 120 Ω"| VRF["VRF"]
    RAIL --> MCU
    VDDA --> MCU
    VRF --> MOD

    MCU["STM32F303RET6<br/>Cortex-M4F @ 72 MHz"]
    MCU <-->|"SPI1 · NSS · BUSY · DIO1 · NRST"| MOD["E22-900M22S<br/>SX1262 · +22 dBm"]
    MCU -->|"RXEN / TXEN"| MOD
    MOD -->|ANT| SMA["SMA edge<br/>J6"]

    MCU <-->|"SPI3 · CS"| FLASH["W25Q128JV<br/>16 MiB flash"]
    MCU <-->|"I²C1"| OLED["128×64 OLED<br/>header"]
    MCU <-->|"SWD + NRST"| DBG["ST-Link<br/>J3"]
    MCU <-->|"GPIO · USART1"| HDR["Edge headers<br/>J5 / J7"]
    BTN["User button<br/>PC13"] --> MCU

📁 Repository layout

IRIS-868/
├── CHANGELOG.md               Release history
├── hardware/
│   ├── kicad/                 KiCad 10 project (schematic, PCB, design rules)
│   │   └── libs/              Source symbols, footprints, 3D models
│   └── gerbers/
│       ├── rev.A/             Gerber and Excellon files, revision A
│       └── rev.B/             Gerber and Excellon files, revision B
├── production/BOM/            Interactive BOM for assembly
└── docs/
    ├── schematics/            Schematic PDF
    ├── images/                Board renders by revision
    └── datasheets/            Component reference documents

The schematic uses four top-level sheets, a KiCad 10 feature: MCU, crystal, reset, VBUS monitor and edge headers (IRIS-868.kicad_sch), power and USB (pwr.kicad_sch), the radio (rf.kicad_sch), and connectors, flash and the user button (interfaces.kicad_sch).

🔧 Hardware overview

Power

USB VBUS feeds an AP2112K-3.3 LDO (SOT-23-5, 600 mA) that generates the single 3.3 V system rail. Three domains branch from it:

The ferrite beads isolate the analog and RF domains from digital switching noise on the main rail, and C7 and C8 sit next to the VDDA pin. The 22 µF bulk capacitor on VRF supplies the current burst drawn by the module during transmission.

VBUS and +3.3 V are both available on header J5, so the board can supply a small carrier or add-on board.

VBUS monitoring

A 47 kΩ / 15 kΩ divider (R6 / R7) scales VBUS onto V_MON (PC0, ADC12_IN6), filtered by C20 (100 nF). The divider ratio is 15 / 62, so 5.0 V on VBUS reads as about 1.21 V, and firmware recovers VBUS as V_MON × 4.133. The divider draws roughly 80 µA from VBUS, and its ~11 kΩ source impedance combined with C20 gives a stable input for the ADC sample-and-hold.

RF chain

The E22-900M22S connects to the MCU over SPI1 plus four control lines. RXEN and TXEN drive the module's internal RF switch and must be managed by firmware around every transmit/receive transition. The antenna net (ANT) leaves the module's stamp-hole RF pad away from the module body and reaches the SMA edge connector as a 7.4 mm, 1.0 mm-wide coplanar trace on F.Cu, over an unbroken ground plane on B.Cu. A project design rule sets a 0.15 mm gap to the surrounding copper, which gives a calculated impedance of about 50 Ω with a 1.51 mm dielectric and εr 4.5. GND vias flank the feed.

Data-logging flash

A Winbond W25Q128JVSIQ (SOIC-8, 208 mil) on the bottom side provides 16 MiB of non-volatile storage on SPI3 (PC10 / PC11 / PC12) with chip select on PD2. The CS line has a 10 kΩ pull-up (R8) so the flash stays deselected while the MCU is in reset. /WP and /HOLD are tied high through R9 and R10, so the device operates in standard single-bit SPI mode; dual/quad I/O is not available on this revision. C21 decouples the flash locally.

User input and reset

USB

The USB D+ 1.5 kΩ pull-up (R2) is connected to PB8 rather than to +3.3 V. Firmware must drive PB8 high to signal device attach to the host, and can drive it low to force a clean disconnect/re-enumeration without unplugging the cable.

Interfaces

Edge headers

J5 and J7 run along the long edges of the board with a row-to-row spacing of 31.75 mm (1.25 in). The header bodies are mounted on the bottom side, so the board can be plugged into a carrier with the components facing up. Pin 1 of each header is at the USB end.

📌 Pin assignment

STM32F303RET6 ↔ E22-900M22S

Module pin 8 (DIO2) is left unconnected in revision B.

STM32F303RET6 ↔ W25Q128JV

📐 Board specification

🧾 Bill of materials

For assembly, open the interactive BOM after downloading it.

[!TIP] Capacitor voltage ratings account for MLCC DC bias derating — class II ceramics lose a large fraction of their nominal capacitance near their rated voltage, so ratings are specified at roughly 4–5× the working voltage. A 2.54 mm jumper shunt on J1 is needed only to enter the bootloader, and it isn't part of the PCB BOM.

🚀 Getting started

git clone https://github.com/StringLess80/IRIS-868.git
cd IRIS-868
kicad hardware/kicad/IRIS-868.kicad_pro

st-flash --reset write firmware.bin 0x08000000

stm32flash -w firmware.bin -v -g 0x0 /dev/ttyUSB0

dfu-util -a 0 -s 0x08000000:leave -D firmware.bin

📦 Releases

The major version changes with each PCB revision. Minor and patch versions cover compatible changes to the BOM, documentation or fabrication outputs. See the changelog for details.