Loop Echo

Loop Echo (working name)

A single-PT2399 delay with an effects loop in the feedback path:

• only the repeats circulate through the loop;
• the first echo is clean, and each later echo goes through the external effect again: fuzz degrades, a filter re-voices, a pitch shifter cascades;
• delay-time modulation (RATE, DEPTH);
• true bypass, plus a LOOP footswitch that switches the effects loop in or out of the repeats.

The PT2399 network is taken from your Small Time (~/Documents/eagle/projects/Small Time/, 2022), without its tails JFET.

• Schematic: docs/LoopEcho_schematic.pdf, generated by scripts/build_loopecho.py. ERC 0.
• Board: LoopEcho.kicad_pcb, from scripts/buildpcb_loopecho.py (don't re-run it after editing the board in KiCad).
• Notes: docs/Design Notes.md.

Controls (v1.0): TIME (B50k), REPEAT (B10k), MIX (B10k), RATE (B1M), DEPTH (B100k), TONE (B50k): six knobs.

Jacks (v1.0): all board-mounted on the top wall of a 1590BB (landscape), outside view left → right: OUT · RETURN · DC · SEND · IN (Tayda A-6728 PJ-646F stereo switched jacks, A-4118 DC jack). RETURN is switched: with no plug, its tip switch ties RETURN to SEND, so the loop closes internally and it's a normal delay.

Status: v1.0 SMD schematic (2026-10-25), to be ordered as a prototype (not breadboarded; the PT2399 network is proven in Small Time). ERC 0. All SMD parts are JLC basic except the PT2399-SN (C126407). Changes from v0.1: SEND / switched RETURN instead of the TRS insert; TONE in the feedback path (B50k + 2k2 into 10n, ~7 kHz-300 Hz, on every repeat, loop or internal); LFO into the TIME / 2k7 node (even depth, Dragonfish) on an LM358; AMS1117-5.0; SS14; status LED + footswitch header. v0.1 generator kept as scripts/build_loopecho_v0.1.py. Board (2026-10-25): LoopEcho.kicad_pcb, 1590BB landscape, 100 × 83.5 mm, two footswitches (LOOP left, BYPASS right; a SwitchPCB v2 on each), routed (re-routed 2026-10-26: supply nets +9V / GND / +5V / VB / D1-A at 0.4 mm, signals 0.25 mm, 88 vias): DRC 0 errors / 0 unconnected, parity clean. Panel layout and drill notes in the Design Notes (Board). Fab files (2026-10-26, after the re-route): production/ (gitignored: attach the zip to a GitHub Release): LoopEcho.zip (Gerbers + PTH/NPTH drill, slots included), bom.csv + positions.csv (75 SMD placements, top side only, 28 lines, all LCSC; only the PT2399 is an extended part), LoopEcho_hand_solder.csv. In JLC's preview check U1 (PT2399) and U5 (SOT-223) rotation; the op-amps carry FT Rotation Offset 270. Drilling: enclosure/README.md. Silk pass done 2026-10-26 (references clear of pads and other silk; Gerbers regenerated): the only DRC warnings left are the jack outlines running past the top edge (by design) and C13's reference touching U2's outline.