Z80-cpu mem

Z80-CPM

RCBus Z80 CPU, 512 KiB SRAM, and 512 KiB Flash ROM module for RCBus systems designed using discrete logic

Table of Content

• Overview
  • Specifications
• Assembly Instructions
• Hardware Documentation
  • Schematic and PCB Layout
  • Input/Output Ports
  • Connectors
  • Bill of Materials
• Release Notes
  • Changes
  • Known Issues
• Red Tape
  • Licensing
  • Trademarks

Overview

Z80-CPM is an RCBus and RC2014* compatible module, designed to run RomWBW firmware including CP/M, ZSDOS, and various applications under these OSes. Z80-CPM combines functionality of the following RC2014* modules on a single module, thus saving space on the backplane:

• Z80 CPU Module
• 512k ROM 512k RAM Module - Simplified version, compatible with RomWBW firmware
• Clock and Reset Module

Minimal CP/M computer system can be built using Z80-CPM module, a backplane, and a serial port module, for example Steve Cousins' SC716 or SC725 Z80 SIO modules, or MC68B50 ACIA. A Compact Flash module can be added for additional storage. For a compact system, a 3-slot SC723 can be used.

Specifications

• Processor: Zilog* Z80 CPU (CMOS version - Z84C00)
• Memory: 512 KiB SRAM, 512 KiB Flash ROM, RomWBW compatible memory pager
• Bus: RCBus, RC2014* compatible
• Microprocessor Supervisor for system reset generation

Assembly Instructions

Please refer to Assembly Instructions document

Hardware Documentation

Schematic and PCB Layout

• Schematic - Version 1.0
• PCB Layout - Version 1.1
• PCB Layout - Version 1.0

Memory Configuration Input/Output Ports

Z80-CPM supports up to 512 KiB of RAM and up to 512 KiB of Flash ROM. It has a simple memory bank switching mechanism with two 32 KiB memory banks, inspired by Steve Cousin's SC602 Memory Module. This memory bank mechanism provides minimal required functionality for the RomWBW RCZ80_std.rom image to be used without any modifications. The upper 32 KiB bank is always mapped to the top 32 KiB of the physical RAM. The lower 32 KiB bank can be mapped to any 32 KiB size page in the physical memory. The memory page is selected by writting either 0x78 or 0x79 I/O ports, that are mapped to the same page select register.

0x78 or 0x79 - Memory Page Select Register (Write-only)

• Notes:
  • The register is reset to '0' on power-on or reset, which maps the lower 32 KiB of the Flash ROM to bank #0.
  • Bit 5 selects between the Flash ROM (bit 5 = 0) and the RAM (bit 5 = 1).

Jumpers Settings

JP1 - RAM Size Configuration

JP2 - Connect on-board oscillator clock to the CPU

JP3 - Connect the RCBus CLK1 signal to the CPU

JP2 and JP3 Configuration Notes

The module supports the following options for the CPU clock:

1. Default: CPU uses the clock frequency generated by the X1 oscillator, and the X1 clock frequency is output to CLK1 signal on RCBus. Install both JP2 and JP3 for this option.
2. CPU uses the clock frequency provided by another module on RCBus. Install only JP3 for this option.
3. CPU uses the clock frequency generated by the X1 oscillator, while other modules use different CLK1 signal. This might be useful, for example, when running the CPU on a frequency other than 7.3728 MHz. Install only JP2 for this option.

Connectors

J1 - RC2014* Bus

Bill of Materials

Version 1.0

Mouser projects - All components except of the PCB and the CPU:

• Z80-CPM project
  • Note that optional CPU supervisor parts: U9 DS1233 CPU supervisor, C11 1 nF capacitor, and SW1 tactile switch are included in this project.

Z80-CPM project on Tindie:

• Complete kit.
• Z80-CPU PCB.

Release Notes

Changes

• Version 1.1

  • Fix cosmetic issues:
    • Swap C5 with C8 and C4 with C6.
    • Modify C10 footpring to clearly show negative terminal.

• Version 1.0

  • Initial version.

Known Issues

• Version 1.0
  • Cosmetic issues:
    • C5 and C8, and C6 and C4 should be swapped.
    • C10 should have more clear marking for the negative terminal.

Red Tape

Licensing

Z80-CPM is an open source hardware project. The hardware design itself, including schematic and PCB layout design files are licensed under the strongly-reciprocal variant of CERN Open Hardware Licence version 2. Documentation, including this file, is licensed under the Creative Commons Attribution-ShareAlike 4.0 International License.

Trademarks

• "RC2014" is a registered trademark of RFC2795 Ltd.
• Other names and brands may be claimed as the property of others.