

Chip tester
FPGA Gateware for Commodore MOS 6530 RRIOT
- Size
- 87.8 × 83.5 mm
- Copper layers
- 2
- Thickness
- 1.6 mm
- Parts
- 8
- Nets
- 75
- Pads
- 156
- Tracks, vias
- 958, 97
- Routed
- Yes
- KiCad
- KiCad 8.0 (file 20240108)
- Created
- 1 Oct 2023
- Updated
- 21 Jul 2026
Overview
Chip tester is an open-source printed circuit board by sajattack, from the sajattack/yo6530 repository on GitHub, published under the MIT licence. It is a 2-layer board of 87.8 × 83.5 mm with 8 parts on 75 nets, routed with 958 tracks and 97 vias.
It belongs with the fPGA and programmable logic and retro computing and games boards and the FPGA and CPLD boards of this library.
README
README.md
Dependencies
- FPGA Toolchain: https://github.com/YosysHQ/oss-cad-suite-build
- Simulator: https://verilator.org/guide/latest/install.html
- C++ toolchain: gcc and gnu make
- Trace Viewer: https://gtkwave.sourceforge.net/
- SPI flash programmer: https://www.flashrom.org/
- Linter: https://github.com/chipsalliance/verible
- Hardware research in dwfpy directory uses a Digilent Digital Discovery, python and the dwfpy library to probe and stimulate a MOS6532, for understanding expected behaviour from real hardware
Target Hardware
https://github.com/daglem/redip-riot
Programming the board using Raspberry Pi (3B) with flashrom
Wiring
| Raspi pin name/num | ReDIP RIOT name/num |
|---|---|
| SCK / 23 | SPI_SCLK / 3 |
| MISO / 21 | SPI_SIO1 / 5 |
| MOSI / 19 | SPI_SIO0 / 7 |
| CE0 / 24 | SPI_CS / 1 |
| GPIO25 / 22 | CDONE / 2 |
| 3v3 / 17 | 3v3 / 8 |
| GND / 20 | GND / 6 |
| GPIO24 / 18 | CRESET / 4 |
make MCS6530_002=1 # build the project
scp build/mcs6530.bin pi@<your-pi's-ip>: # copy the build artifact to the pi for flashing
ssh pi@<your-pi's-ip> # connect to the pi
sudo raspi-config # go into the interfaces menu and enable spi after running this command
pinctrl set 24 op dl # put the board into programming mode by setting creset low
flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=20000 # if this detects the device, all is good, otherwise check your spi is enabled and your wiring
truncate -s 128K mcs6530.bin # pad the rom to 128K
flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=20000 -w mcs6530.bin # write the flash
pinctrl set 24 ip pu # exit programming mode by returning creset to input pullupBuilding and running the simulation tests
make MCS6530_002=1 sim
./obj_dir/Vverilator_top # this will throw assertion errors if the tests failAlso you can examine the logic signals output during the test in the Vverilator_top.vcd file using GTKWave
Parts
8| Qty | Value | Footprint | References |
|---|---|---|---|
| 2 | Conn_02x03_Odd_Even | Connector_PinHeader_2.54mm:PinHeader_2x03_P2.54mm_Vertical | J4, J5 |
| 2 | Jumper_2_Bridged | Jumper:SolderJumper-2_P1.3mm_Bridged_RoundedPad1.0x1.5mm | JP1, JP2 |
| 1 | Conn_02x12_Counter_Clockwise | Connector_PinHeader_2.54mm:PinHeader_2x13_P2.54mm_Vertical | J6 |
| 1 | Conn_02x16_Odd_Even | Connector_PinHeader_2.54mm:PinHeader_2x16_P2.54mm_Vertical | J3 |
| 1 | Conn_02x20_Counter_Clockwise | Socket:3M_Textool_240-1288-00-0602J_2x20_P2.54mm | J1 |
| 1 | Conn_02x21_Odd_Even | Connector_PinHeader_2.54mm:PinHeader_2x21_P2.54mm_Vertical | J2 |
Questions
How big is the Chip tester PCB?
It measures 87.8 × 83.5 mm and has 2 copper layers, 1.6 mm thick.
What parts does the Chip tester use?
8 parts. The full list of its parts is on this page, with links to each part's symbol and footprint where PCBKit's library has them.
Where can I download the Chip tester KiCad files?
From the sajattack/yo6530 repository on GitHub, at the commit this page was made from: the board is hw_tester/mega2560_pro/hw/kicad/chip_tester.kicad_pcb and its schematic hw_tester/mega2560_pro/hw/kicad/chip_tester.kicad_sch. PCBKit opens the board in the browser, with nothing to install.
Can I use the Chip tester design in my own project?
Its repository publishes it under the MIT licence: you may reuse it on that licence's terms (keep the author's notice, and for a copyleft licence share your changes alike).
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