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Passive Compute Blade to Dark Dragons Astronomy GPS/RTC adapter PCB
Compute blade dda adapter is an open-source printed circuit board by rritterson, from the rritterson/computeblade-adapter repository on GitHub. It is a 2-layer board of 49 × 16 mm with 2 parts on 10 nets, routed with 364 tracks and 0 vias.
It is built around the HLE-105-02-L-DV-PE-BE and MTLW-106-05-G-D-140. It belongs with the interfaces and adapters and radio and wireless boards of this library.
This repository contains a passive two-connector KiCad adapter that remaps the Dark Dragons Astronomy GPS PPS signal while keeping the unmodified DDA PCB parallel to the Compute Blade PCB. Physical connector pin numbers are authoritative; GPIO names are descriptions and are never interpreted as BCM pin numbers.
The project targets KiCad 10.0.5 through the pinned kicad/kicad:10.0.5-full CI image.
Passing connectivity, ERC, DRC, CAD collision, and clearance checks is required but does not make this design fabrication-ready. Connector seating forces and final BladeRunner fit still require a physical prototype.
HLE-105-02-L-DV-PE-BE, 2×5, 2.54 mm, bottom-entry/pass-through receptacle.MTLW-106-05-G-D-140, 2×6, 2.54 mm, conventionally mounted vertical male header; its manufacturer-designated gold-plated mating post points toward the DDA.The exact footprints are project-local in pcb/Adapter.pretty/. They use the manufacturer 2.54 mm patterns, explicit fab outlines, courtyards, 1.0 mm drills, and 1.8 mm pads. That gives a nominal 0.40 mm annular ring. The 1.0 mm board provides a conventional, stiff interposer, but the selected fabricator must still confirm 1.0 mm FR-4, 1.0 mm plated drills, and its finished-hole/annular-ring rules before ordering.
The generated connector STEP models are manufacturer-dimensioned approximations because exact configured Samtec CAD is not available to deterministic unauthenticated CI. They are not substitutes for a first-article fit test.
X = Compute Blade long axis
Y = Compute Blade width
Z = outward normal from the Compute Blade PCB
Compute Blade PCB plane = XY
adapter PCB plane = XY
DDA PCB plane = XY
DDA PCB normal = +Z
DDA socket mating axis = -Z toward adapter
J2 mating posts = +Z
J2 six-position axis = +X
J2 row 1 → row 2 = -YThe shared DDA transform is the identity basis:
[[1, 0, 0],
[0, 1, 0],
[0, 0, 1]]scripts/design_config.py is the sole parameter source used by the PCB generator, geometry validator, STEP generator, SVG generator, and PNG renderer. Unit tests hard-fail if the DDA becomes upright, the GNSS face points inward, the mating direction reverses, or J2’s columns/rows change axes.
| Physical pin | J1 Compute Blade | J2 DDA | Adapter net |
|---|---|---|---|
| 1 | 3V3 | 3V3 | 3V3 |
| 2 | 5V | unused by DDA | 5V_PIN2 |
| 3 | GPIO2 / SDA | SDA | SDA_GPIO2 |
| 4 | 5V | unused by DDA | 5V_PIN4 |
| 5 | GPIO3 / SCL | SCL | SCL_GPIO3 |
| 6 | GND | GND | GND_PIN6 |
| 7 | GPIO4 / PPS_IN | unused DDA position | PPS_GPIO4 |
| 8 | GPIO14 / UART_TX | GPS_RX | UART_TX_TO_GPS_RX |
| 9 | GND | unused by DDA | GND_PIN9 |
| 10 | GPIO15 / UART_RX | GPS_TX | UART_RX_FROM_GPS_TX |
| 11 | — | RTC_INT | NC |
| 12 | — | GPS_PPS | PPS_GPIO4 |
Pins J1.1–J1.10 map one-for-one to J2.1–J2.10. J2.12 additionally joins J1.7/J2.7, so GPS PPS reaches Compute Blade physical pin 7 / GPIO4. J2.11 remains explicitly unconnected. Duplicate rails remain separate: 5V_PIN2, 5V_PIN4, GND_PIN6, and GND_PIN9 are not merged by the adapter.
Physically measured Compute Blade dimensions:
Manufacturer HLE requirements:
J1_SEATING_GAP_MM = 0.350 is the single authoritative gap between the Compute Blade header-plastic top and adapter/J1 seating plane.-PE-BE is open/pass-through, so excess post does not bottom in a closed socket.The same exact connector Z-chain was evaluated at all requested gaps:
| Seating gap | Adapter underside | J1 required reach | J1 surplus | J2 tail clearance | Outward stack | Physical clearance | Margin after reserve |
|---|---|---|---|---|---|---|---|
| 0.300 mm | 2.800 mm | 3.890 mm | 2.610 mm | 0.366 mm | 17.776 mm | 2.1557 mm | 1.1557 mm |
| 0.350 mm | 2.850 mm | 3.940 mm | 2.560 mm | 0.416 mm | 17.826 mm | 2.1057 mm | 1.1057 mm |
| 0.400 mm | 2.900 mm | 3.990 mm | 2.510 mm | 0.466 mm | 17.876 mm | 2.0557 mm | 1.0557 mm |
The preferred 0.350 mm value passes every hard gate while retaining more BladeRunner margin than 0.400 mm and giving more tail clearance than 0.300 mm.
Manufacturer MTLW geometry:
OAL 8.510 mm
insulator 1.520 mm
designated -140 mating post 3.556 mm
solder tail 3.434 mm
DDA insertion 3.400 mm
free post after insertion 0.156 mm
lower solder-tail tip above blade PCB 0.416 mmMTLW-106-05-G-D-140 uses the normal manufacturer orientation: the -140 post is the DDA mating end and receives the specified 10 µin gold plating; the opposite 3.434 mm segment is the solder tail. Samtec lists this exact configuration in its Reserve program. See the exact Samtec product page and official MTLW series print.
Measured DDA geometry:
The 4.0 mm value already includes the 1.6 mm PCB. It must not be calculated as 1.6 + 4.0.
adapter underside 2.850 mm
+ adapter PCB 1.000 mm
+ MTLW insulator 1.520 mm
+ unused designated post after insertion 0.156 mm
= DDA socket mating face 5.526 mm
+ mating face to socket-side PCB surface 8.300 mm
+ socket-side surface to GNSS top 4.000 mm
= total outward stack 17.826 mmThe official Compute Blade STEP anchors J3 at (133.075077, 18.325065, 0.0) mm. The selected complete DDA projection is:
X = 160.000 .. 176.500 mm
Y = 19.500 .. 42.000 mmThe validator extracts the official PCB solid bounds from the STEP and requires the full DDA PCB, socket, GNSS envelope, and inward battery envelope to remain inside its XY footprint with a 0.5 mm configured margin.
BladeRunner clearance uses the physical slit-edge result, not slit centerline pitch:
physical per-blade clearance 19.9317 mm
safety reserve 1.0000 mm
design maximum 18.9317 mm
approved outward stack 17.8260 mm
physical nominal clearance 2.1057 mm
margin after 1.0 mm reserve 1.1057 mmCI authenticates the pinned official half body.stl, rechecks its mesh encoding, triangle count, hash, and outer bounds, and applies the previously slit-edge-derived 19.9317 mm physical clearance. It does not substitute the obsolete (-1.5, 45.0) clearance box or the former 36 mm total-depth rule.
scripts/fetch_reference_cad.py authenticates upstream CAD at immutable Compute Blade commit 9c7e472f4fb5c74401d17cdc7a766254d78a32c6:
models/blade/v1.0-mk4/v1.0_mk4_DEV.stepmodels/bladerunner/19-inch/half body.stlmodels/bladerunner/19-inch/left bracket.stlmodels/bladerunner/19-inch/right bracket.stlPure-Python validation checks the shared transforms, pin-1 mapping, designated J2 mating end, connector reach, 3.40 mm insertion, the 0.30 mm minimum tail clearance, DDA XY keep-in, 17.826 mm stack, 2.00 mm minimum physical clearance, and 1.00 mm minimum post-reserve margin. The CadQuery assembly stage additionally intersects the DDA, J2, and adapter-outside-J1 region against the exact official Compute Blade B-Rep and fails on material overlap.
The confirmed DDA pin-1 orientation remains:
This is encoded independently of electrical net names.
scripts/generate_assembly_model.py produces:
mechanical/generated/full_assembly.stepmechanical/generated/full_assembly_lightweight.stepmechanical/generated/full_assembly_with_bladerunner.stepThe full assembly imports the exact official Compute Blade B-Rep. The BladeRunner-context assembly adds the validated 18.9317 mm design plane and 19.9317 mm physical-clearance plane. All placement uses the same boxes and transforms as validate_geometry.py; there is no separate visual-only placement.
Open the STEP files in FreeCAD. From a successful GitHub Actions run, download the compute-blade-dda-adapter-reports artifact for the STEP files, fixed renders, manifests, ERC/DRC reports, and board views. The visual model is an inspection aid and does not replace a physical prototype.
python3 scripts/fetch_reference_cad.py
python3 scripts/generate_schematic.py
python3 scripts/generate_or_update_pcb.py
python3 scripts/generate_mechanical_model.py
python3 scripts/verify_connectivity.py
python3 -m unittest discover -s scripts -p 'test_*.py' -v
python3 scripts/validate_geometry.py
python3 -m pip install --requirement requirements-assembly.txt
python3 scripts/generate_assembly_model.pyGitHub Actions repeats deterministic generation, connectivity verification, unit tests, geometry validation, STEP round-trip checks, blank-render checks, KiCad ERC/DRC, Gerber export, and Excellon drill export. Download compute-blade-dda-adapter-manufacturing for compute-blade-dda-adapter-gerbers.zip; the BOM is included in compute-blade-dda-adapter-reports.
The project must not be described as fabrication-ready until those physical checks are closed.
| Qty | Value | Footprint | References |
|---|---|---|---|
| 1 | HLE-105-02-L-DV-PE-BE | Adapter:Samtec_HLE-105-02-L-DV-PE-BE | J1 |
| 1 | MTLW-106-05-G-D-140 | Adapter:Samtec_MTLW-106-05-G-D-140 | J2 |
It measures 49 × 16 mm and has 2 copper layers, 1 mm thick.
2 parts, built around the HLE-105-02-L-DV-PE-BE and MTLW-106-05-G-D-140. The full list of its parts is on this page, with links to each part's symbol and footprint where PCBKit's library has them.
From the rritterson/computeblade-adapter repository on GitHub, at the commit this page was made from: the board is pcb/compute-blade-dda-adapter.kicad_pcb and its schematic pcb/compute-blade-dda-adapter.kicad_sch. PCBKit opens the board in the browser, with nothing to install.
Its repository states no licence, so its author keeps all rights: ask rritterson before reusing the design.

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