MAXwel

MAXwel

MAX ii Workbench for Education and Learning - MAXwel

MAXwel is a cheap and simple FPGA development board made for educational purposes. It is based in a low-cost Altera MAX ii Chip (EPM240), containing 240 logic elements, 8Kbits of RAM and 32Kbits of flash memory. The board is equipped with 8 switches, 4 push-buttons, 16 LEDs (divided into rows A and B of 8 LEDs each) and four 7-segment displays. It also contains a 50MHz oscillator and a 14,7456 MHz oscillator as a clock source. The board is programmed through a USB Blaster JTAG interface with the pin-header located on the board.

All schematics and PCB files are available in the hardware directory.

Documentation and project template

The user documentation is available in the docs directory and on the landing page.

A template for an empty VHDL project with correct pin assignments is available in the template directory. The directory also contains a template for a schematic based circuit design. All templates are intended to be used with the Quartus software from Intel.

What else?

There are also some features for hardcore enthusiasts.

Lab Course

My university uses this FPGA board for a students lab course. There is a directory containing the reference designs for the lab course exercises. The lab course exercises require the students to draw schematic diagrams in the Quartus software within a predefined template file. The Quartus software only offers the logic symbols in the US style within the schematic editor. This directory also offers EU style symbols for the project symbol library of the Quartus software.

Overlay

This project is currently under heavy development.

The Overlay is an open FPGA architecture for open tools and user designs that is intended to run on the MAX ii chip, in essence an "FPGA on a FPGA". The main goal of the Overlay is to provide a simple and easy to use platform for learning and experimenting with FPGA synthesis technology. Once the overlay is synthesizes and loaded into the MAX ii chip, it will be possible to load user designs into the overlay, without the need to re-synthesize the overlay itself. This allows for a high level of flexibility and experimentation, as well as a way to learn about FPGA synthesis and design without the need for the closed source tools from the FPGA manufacturer. Emulating an FPGA inside an FPGA takes up a lot of resources. Therefore the Overlay is not made for practical use cases outside of learning and experimentation.