Pico thing

Pico-Thing

An 8-bit MC6809E / HD6309E single-board computer with a pair of Raspberry Pi Pico 2 (RP2350 / Pimoroni PGA2350) modules acting as intelligent bus peripherals, a 1–2 MB banked-RAM DAT/MMU, a 40-pin PATA hard-disk interface, and an HSTX→DVI video output.

The board is entirely through-hole where it matters — old-school sockets, hand-solderable, KiCad 10 project.

Pre-release — v2.0 work-in-progress. This snapshot has not been fabricated end-to-end. Individual blocks are at different maturity levels, and several are known to be untested on real hardware: the real-time clock, the LCD interface, the revised v2.0 power arrangement (external +VDC input + MIC29501 5 V rail switched by A101), the external USB-A input, the EMC ferrites, and the top-level sheet reorganisation are all fresh since the last spun board. Look for (untested) markers on the sections below.

The last hardware that was actually fabricated and partially tested lives on the RELEASE_1.0 branch — read its notes before assuming any v2.0 change is known-good. Bring-up and OS-port work is being done against the usim simulator in parallel.

Repository layout

Branches

• main — work-in-progress v2.0. Substantial rework: video subsystem redesigned around the PGA2350 (firmware moved to ../pico-thing-video), power section redone with an external +VDC input and a MIC29501 5 V linear rail, ATA/HD terminal block moved onto the ATA sheet, ferrite beads added to the peripheral supplies, DAT/MMU control split across two GALs on the RAM_and_DAT sheet, and generous new test points wired up for bring-up and scope work.
• RELEASE_1.0 — the last hardware that has actually been spun and partially tested. Contains my working notes on what needs to be fixed, what needs to be re-tested, and the migration path to v2.0. Read this branch before touching a v1.0 board.

Design highlights

CPU and its two RP2350 companions

• U102 — MC6809E in a 40-pin socket, or drop-in HD6309E for the extended register set / faster instruction timings. Real silicon, real bus timing.
• A101 — Pimoroni PGA2350 module sitting next to the CPU. A101 sources the E and Q clocks that drive the 6x09 — the CPU's bus timing is generated by A101's PIO, not by an external crystal oscillator. It also behaves as a slave bus peripheral: it watches A/D/control lines via PIO state machines and responds when its !CS is asserted, presenting a memory-mapped register window that the 6809 can read and write. This is where firmware-emulated devices (serial ACIAs, storage helpers, boot-ROM loading, host-side gadgets) live. !RESET is observed; !IRQ is driven back to the CPU as a simulated open-collector. Firmware lives in the sibling repo ../pico-thing-main.
• A601 — a second PGA2350 dedicated to video. It observes the E/Q clocks that A101 produces, uses the RP2350's HSTX peripheral to drive a DVI-over-HDMI output at 1024×480 RGB332 ~60 Hz, and presents a $FF10-page register window so the 6809 can eventually drive text/graphics from software. Firmware lives in the sibling repo ../pico-thing-video.

DAT RAM architecture

The memory system is a poor-man's 6809 MMU built out of static RAM and two 22V10 GALs (U208, U209) on the RAM_and_DAT sheet. It gives the 6809 a 21-bit physical address space (2 MB) paged into its native 16-bit logical space in 8 kB pages:

• Logical $0000–$DFFF — 7 fully translated pages. Each page's physical address (PA13..PA20) comes from the DAT RAM, indexed by the logical page number and the current task. The DAT RAM is itself accessible as ordinary RAM at logical $FE00–$FEFF, but only by task 0 (the supervisor).
• Logical $E000–$FFFF — always mapped to physical $1FE000–$1FFFFF regardless of the current task, so the OS, vectors and I/O window are always reachable. This is the ~MMU_fixed signal handled by the GALs.
• If the DAT translates a page to all-ones (i.e. "no page mapped here"), the GAL asserts ~NMI on the CPU. Touching unmapped RAM is a fault, not a silent bit-bucket.

Two AS6C4008-55PCN 512K×8 SRAMs (U203, U204) on the main board provide 1 MB of physical memory; two more of the same on the mezzanine daughterboard bring this up to the full 2 MB.

PATA IDE interface

J401 is a 40-pin IDC header for a standard PATA hard drive (2.5" or 3.5", laptop/desktop, master or slave). The 6809 only has an 8-bit bus and can't do the ATA 16-bit data-register reads natively, so a pair of 74ABT652 bidirectional registered transceivers (with the two data GALs) implement:

• 8-bit register reads/writes for the ATA task-file registers (status, command, LBA0..3, error, features, etc.) — packed into contiguous 6809 address space with no wasted locations.
• 16-bit word reads/writes on the data register, transparently swapped and latched to fit into two consecutive 8-bit 6809 cycles. This means that 16-bit loads and stores to the data register can be done naturally in single instructions.

Host-side memory map is $FF00–$FF09 (one location offset from canonical ATA, with the DEV bit selecting master/slave inside the firmware). An absent drive slot reads status = $00.

Hard-drive power is a Metz-Connect terminal block (J402) on the ATA sheet, filtered through an axial ferrite bead (FB401) from the main +5 V rail, with a hardware ~Reset_HD line driven by the board's power-on-reset supervisor.

Real-time clock (untested)

U106 is a Maxim/Dallas DS12885 — an ISA-era RTC + CMOS RAM part with an external battery-backup pin. J108 is a 2-pin header for the backup battery (a CR2032 holder off-board is the expected fit); the RTC keeps time and preserves its scratchpad RAM across full board power-down. A ~Reset_RTC from the power-on-reset supervisor makes sure the RTC comes up cleanly after each cold start. This block has not been tested on real hardware yet.

LCD interface (untested)

J110 is a 1×16 pin socket carrying the classic HD44780-style parallel LCD signal set (DB0..DB7, RS, R/W, E, backlight and contrast, ground and +5 V). Any 16-pin HD44780-compatible module — 16×2, 20×4 and friends — should drop straight in. RV101 is a small vertical trim pot for the contrast pin (marked DNP in the BOM; solder one on only if your chosen module needs it). Untested on real hardware.

Power (v2.0)

• +VDC — external DC input via a barrel jack; nominally 7.5–12 V.
• +5V (main) — the big logic rail, is generated by a heatsunk MIC29501-5.0 low-dropout linear regulator (U104). This rail is switched under A101's control — A101 owns the enable pin, so firmware on the CPU-side Pico decides when to bring the 6809 side of the board up (or drop it, e.g. for a controlled reset or a fault response). This also powers all of the non-A101 peripherals.
• +5VP — auxiliary/peripheral 5 V rail from a MIC29150WT (U104) in a heatsunk TO-220-5 package. A101 itself runs off this rail so it stays alive across a switch-off.
• +3.3V — local rail on each PGA2350, generated by the Pico modules themselves.
• Downstream peripheral supplies (Video +5V, ATA +5V) are individually ferrite-bead filtered from the +5V rails.
• A 5V-sense divider into an ADC on A101 lets the firmware notice when a rail is sagging and take defensive action.

Test points

v2.0 adds a generous set of test points across the board: TP603/TP604 (video RD/WR), TP605/TP606 (video GND returns), TP116 (+3.3 V local), TP117 (E clock), and the usual GND loops. If you have a scope, you can reach anything interesting without prodding a DIP leg.

Assembly notes

The board is deliberately through-hole and hand-solderable almost everywhere — sockets, DIPs, axial resistors, radial capacitors, IDC headers. The two SMD pockets to be aware of are both in the video area, and both are on the top of the board.

• The HDMI receptacle (J605, Molex 208658-1001) has a fine pin pitch and shielded body — you want a fine tip, flux, and patience. Solder-paste + hot air is easier than iron work here.
• The CAT16-271J4LF HDMI data-line series-terminator arrays (RN601, RN602) are 4×1206 SMD parts. These are the "data resistors" for the differential pairs; the footprint is the hand-solder variant, but they're still small.

Everything else can be built with a plain iron.

Documentation

Everything renderable lives under docs/.

Hand-authored explainer

• docs/dat-mmu.pdf — DAT MMU deep-dive: Task/Block bit-field walkthrough, full DAT RAM diagram, four worked lookup examples (valid page, valid mapped page, unmapped-page NMI, and the hard-wired $1FE000–$1FFFFF window). Source alongside: docs/dat-mmu.tex (LaTeX + TikZ, newtxtext/newtxmath + inconsolata).

Fabrication + reference artefacts

Main board:

• docs/pico-thing-schematic.pdf — multi-sheet schematic PDF
• docs/pico-thing-pcb.pdf — layer plot, one page per layer (F.Cu, In1.Cu, In2.Cu, B.Cu, silk, mask, paste, Edge.Cuts)
• docs/pico-thing-pcb-front.pdf — composite front view (copper + silk + mask + paste + adhesive, drill markers)
• docs/pico-thing-pcb-back.pdf — composite back view, mirrored so B.Silkscreen reads right way round
• docs/pico-thing-pcb-fab.pdf — front fabrication view (Edge.Cuts, F.Silkscreen, F.Courtyard, F.Fab)
• docs/pico-thing-bom.csv — flat CSV BOM, grouped by Value+Footprint, DNPs marked
• docs/pico-thing-gerbers.zip — Gerbers + Excellon drill files + drill map — hand this to your fab

Mezzanine daughterboard — same set with the mezzanine- prefix:

• docs/mezzanine-schematic.pdf
• docs/mezzanine-pcb.pdf
• docs/mezzanine-pcb-front.pdf
• docs/mezzanine-pcb-back.pdf
• docs/mezzanine-pcb-fab.pdf
• docs/mezzanine-bom.csv
• docs/mezzanine-gerbers.zip

Regenerate with docs/build.sh after changing the schematic or PCB. Needs KiCad 10 (defaults to /Applications/KiCad/KiCad.app/Contents/MacOS/kicad-cli on macOS; override with KICAD_CLI=/path/to/kicad-cli ./docs/build.sh).

Simulator

Bring-up, boot-code development and OS work happens against a software model of this board before it touches copper. The simulator is:

• usim — an MC6809/HD6309 cycle simulator with a Pico-Thing hardware profile (dual MC6850-shaped console/aux ACIAs, DAT/MMU, PATA task-file, usim09pt and usim09batch entry points).
• Local checkout: ~/GitHub/usim
• Published at: https://github.com/mrvmurray/usim

The usim09pt --aux-pty mode exposes the aux serial port as a host pseudo-terminal (typically /dev/ttys00N), which is handy for DriveWire and other host-side serial protocols during OS porting.

Related projects

• ../pico-thing-main — firmware for the CPU-side PGA2350 (A101): E/Q clock generation, bus-slave register window, firmware-emulated peripherals (ACIAs, storage helpers, boot-ROM loading). Published at https://github.com/markrvmurray/pico-thing-main.
• ../pico-thing-video — firmware for the video PGA2350 (A601): HSTX→DVI engine, bus-slave register window, Spleen-font text overlay.
• ../usim — cycle-accurate 6809/6309 simulator with Pico-Thing hardware model.

Prerequisites

• KiCad 10 to open the schematic and PCB.
• lwtools (lwasm, lwlink) to build any of the boot ROMs or GAL programming aids.
• A CUPL toolchain (WinCUPL or equivalent) is only needed to rebuild the GAL fuse maps — the current .jed files ship alongside their .PLD sources in GAL/, ready to burn onto the appropriate 22V10 or 16V8 with your usual programmer (Atmel ATF, Lattice GAL, or any other compatible-family part — the JEDEC file is the same; only the programmer's device selection differs).

License

Hardware: see LICENSE.txt.