4 layers33.7 × 12.4 mm
Display eval short
byrantech/laptop
anyon_e, a highly integrated, high end, open source laptop. Attempt the impossible.
4 parts4.3kMIT
4 layers30 × 20 mm
Pdn test
markomij12/PDN-CoSimulationKiCad → openEMS validator → SPICE / plane PDN optimizer (decap BOM + |Z(f)|)
- Size
- 30 × 20 mm
- Copper layers
- 4
- Thickness
- 1.6 mm
- Parts
- 4
- Nets
- 2
- Pads
- 8
- Tracks, vias
- 0, 6
- Pours
- 2
- Routed
- Not yet
- KiCad
- KiCad 8.0 (file 20240108)
- Created
- 14 Aug 2026
- Updated
- 17 Sep 2026
Overview
Pdn test is an open-source printed circuit board by markomij12, from the markomij12/PDN-CoSimulation repository on GitHub, published under the MIT licence. It is a 4-layer board of 30 × 20 mm with 4 parts on 2 nets.
Its parts include 3 capacitors and 1 IC.
README
boards/README.mdBoards
Phase 1 is still the analytical plate in em_extraction.geometry, not a layout file.
Phase 2 board: pdn_test.kicad_pcb — a small 4-layer FR-4 coupon for the KiCad → openEMS bridge. You don't need the KiCad GUI; read_board() parses the s-expression in the project venv.
pdn_test.kicad_pcb
| Item | Value |
|---|---|
| Size | 30 mm × 20 mm (Edge.Cuts rectangle at the origin) |
| Stackup | 1.6 mm FR-4-ish, 35 µm copper |
| F.Cu / B.Cu | signal (unused by the extractor) |
| In1.Cu | VCC power plane |
| In2.Cu | GND plane |
| Inner dielectric | 0.2 mm prepreg, εr = 4.5 (the PDN cavity, In1.Cu ↔ In2.Cu) |
| Core | 1.04 mm, εr = 4.5, F.Cu↔In1.Cu |
| Bottom prepreg | 0.2 mm, εr = 4.5, In2.Cu↔B.Cu |
The .kicad_pcb text file stores millimetres (KiCad's internal unit is nm). em_extraction.kicad_reader.read_board converts millimetres → metres in BoardGeometry.
Net / footprint convention
read_board() identifies ports by names, not hardcoded xy:
| Role | How it is identified |
|---|---|
| Power net | VCC |
| Ground net | GND |
| IC power pin | footprint reference U1, pad on net VCC |
| Candidate decap sites | vias on net VCC |
U1 is a dummy 2-pin load (pad 1 = VCC, pad 2 = GND). C1 and C2 sit next to U1; C3 is farther out so the optimizer has a near/far placement choice. Move a VCC via in KiCad and re-run python run_pipeline.py --board boards/pdn_test.kicad_pcb to change the extracted S-parameters.
To add another decap candidate, place a via on net VCC. To move the IC pin, move footprint U1.
Parts
4| Qty | Value | Footprint | References |
|---|---|---|---|
| 3 | C | Capacitor_SMD:C_0603_1608Metric | C1, C2, C3 |
| 1 | LOAD | PDN:Load_2pin | U1 |
Similar boards
- 4 layers78 × 40 mm
Add on template
dotstartech/wall-panel
Wall mounted 4 inch touch display panel with CM4 inside
4 parts445 - 4 layers48.5 × 16.3 mm
- 4 layers27.5 × 25 mm
- 4 layers80 × 40 mm
Init file
Hongcheng-Gao/EngiWorld
Engiworld: What Can Frontier Agents Deliver in Professional Engineering Environments?
4 parts52MIT - 4 layers44.5 × 59.5 mm
Breadboard adapter
OpenDevicePartnership/pico-de-gallo
A tool for testing Embedded Rust drivers for discrete I2C/SPI components.
4 parts21MIT - 4 layers28 × 17 mm
Jtag swd bridge
azonenberg/misc-devboards
Miscellaneous prototype hardware that wasn't major enough to warrant a dedicated repo
4 parts17BSD-3-Clause - 4 layers22 × 30 mm
Questions
How big is the Pdn test PCB?
It measures 30 × 20 mm and has 4 copper layers, 1.6 mm thick.
What parts does the Pdn test use?
4 parts. The full list of its parts is on this page, with links to each part's symbol and footprint where PCBKit's library has them.
Where can I download the Pdn test KiCad files?
From the markomij12/PDN-CoSimulation repository on GitHub, at the commit this page was made from: the board is boards/pdn_test.kicad_pcb. PCBKit opens the board in the browser, with nothing to install.
Can I use the Pdn test design in my own project?
Its repository publishes it under the MIT licence: you may reuse it on that licence's terms (keep the author's notice, and for a copyleft licence share your changes alike).