4 layers56.1 × 57.1 mm
MCL86jr
MicroCoreLabs/Projects
Ted Fried's MicroCore Labs Projects - FPGA CPU cores and emulators for the 8088, 8086, 8051, 6502, 68000, Z80, Risc-V, and also Typewriter and EPROM Emulator projects.
66 parts534
2 layers48 × 53.3 mm
ESP32 LogicAnalyzer
lmcapacho/ESP32_LogicAnalyzer28Low-cost logic analyzer using ESP32 for fast digital signal debugging
- Size
- 48 × 53.3 mm
- Copper layers
- 2
- Thickness
- 1.6 mm
- Parts
- 12
- Nets
- 48
- Pads
- 105
- Tracks, vias
- 184, 17
- Pours
- 1
- Routed
- Yes
- KiCad
- KiCad 9.0 (file 20241229)
- Created
- 30 Jan 2025
- Updated
- 10 Jul 2026
Overview
ESP32 LogicAnalyzer is an open-source printed circuit board by lmcapacho, from the lmcapacho/ESP32_LogicAnalyzer repository on GitHub, published under the GPL-3.0 licence. It is a 2-layer board of 48 × 53.3 mm with 12 parts on 48 nets, routed with 184 tracks and 17 vias.
It is built around the SN74LVC245APW. Its parts include 4 resistors, 4 connectors, 2 capacitors and 2 ICs. It belongs with the sensors and measurement boards and the ESP32 boards of this library.
Main components
1README
README.mdESP32 LogicAnalyzer
A SUMP compatible 16Bit Logic Analyzer for ESP32 MCUs.
Specifications
- Uses ESP32 I2S DMA and can capture speeds up to 20 MHz.
- Supports 8-bit and 16-bit operations.
- Maximum 128k samples (even in 8-bit capturing mode).
- RLE compression supported.
- Default OLS port is UART0 with a default baud rate of 912600.
- You can configure UART ports and high-speed baud rates for OLS communication by editing the definitions in LogicAnalyzerConfig.h.
Supported Environments
| Environment | Status | Details |
|---|---|---|
| PlatformIO | ✅ | Tested with platform-espressif32@6.11.0 |
| Arduino IDE | ✅ | Tested with Arduino-ESP32 core 3.3.7 |
Under Development
- WROOVER modules support 2M samples but only up to 2 MHz due to bandwidth limits on PSRAM access.
- Analog input support.
Quick Start Guide
Environments
PlatformIO
- Install PlatformIO in VS Code.
- Open the project folder in PlatformIO.
- Build the project and flash it to your ESP32.
Arduino IDE
- Install the ESP32 board support via the Boards Manager (
esp32 by Espressif Systems). - Open the sketch in
ESP32_LogicAnalyzer/ESP32_LogicAnalyzer.ino. - Select the board you're using (e.g.
ESP32 Dev Module). - Use ESP32 Arduino core version
3.3.7. - Click Upload.
Important: If you're using UART0 for OLS communication, set Core Debug Level = None in the Arduino IDE before compiling, especially for captures above 10 MHz.
PulseView
Open PulseView with:
pulseview -D -d ols:conn=/dev/ttyUSB0::serialcomm=921600/8n1Or from the GUI, connect the device and select Openbench Logic Sniffer & SUMP compatibles (ols).
RLE can be enabled in Device configuration dialog:
For more details, see the PulseView documentation.
Connections
| Pin | Connection |
|---|---|
| clk_in | GPIO23 (connect to clk_out) |
| clk_out | GPIO22 (connect to clk_in) |
| Ground | Connect the target device's GND to the ESP32 GND |
| Channels | CH15 - CH0 (connect your signals here) |
⚠️ Warning: GPIO23 is used for I2S input clock and GPIO22 for LEDC output clock.
Do not use these pins for general I/O. If needed, change them in the code and rewire accordingly.
Hardware Design (KiCad)
This project includes a custom PCB designed in KiCad 9 to connect the ESP32 DevKitC V1 with logic analyzer channels and level shifters.
All hardware-related files are located in the hardware/ folder and include:
- Complete KiCad project (
.kicad_pro,.kicad_sch,.kicad_pcb) - BOM (
BOM.xlsx) and CPL (CPL1.xlsx) for assembly - Gerber files (
hardware/gerbers/) for PCB fabrication - Optional UART2 debug port
- Level shifter ICs (SN74LVC245A) for 5V input compatibility
⚠️ The design is currently under validation. Use at your own risk until physical tests are completed.
PCB Preview
Attributions
This project is a fork of ESP32_LogicAnalyzer, created by Erdem U. Altinyurt.
This project uses code from:
- esp32-cam-demo for I2S DMA.
- Arduino Logic Analyzer as a SUMP protocol "template".
License
This project is licensed under the GPL 3.0 License. See the LICENSE file for details.
Parts
12| Qty | Value | Footprint | References |
|---|---|---|---|
| 4 | 10K | Resistor_SMD:R_0603_1608Metric | R1, R2, R3, R4 |
| 2 | 100n | Capacitor_SMD:C_0603_1608Metric | C1, C2 |
| 2 | Conn_01x15 | Connector_PinSocket_2.54mm:PinSocket_1x15_P2.54mm_Vertical | J1, J2 |
| 2 | SN74LVC245APW | Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm | U1, U2 |
| 1 | CHANNELS | Connector_PinHeader_2.54mm:PinHeader_2x10_P2.54mm_Vertical | J3 |
| 1 | DEBUG | Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical | J4 |
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Questions
How big is the ESP32 LogicAnalyzer PCB?
It measures 48 × 53.3 mm and has 2 copper layers, 1.6 mm thick.
What parts does the ESP32 LogicAnalyzer use?
12 parts, built around the SN74LVC245APW. The full list of its parts is on this page, with links to each part's symbol and footprint where PCBKit's library has them.
Where can I download the ESP32 LogicAnalyzer KiCad files?
From the lmcapacho/ESP32_LogicAnalyzer repository on GitHub, at the commit this page was made from: the board is hardware/ESP32_LogicAnalyzer.kicad_pcb and its schematic hardware/ESP32_LogicAnalyzer.kicad_sch. PCBKit opens the board in the browser, with nothing to install.
Can I use the ESP32 LogicAnalyzer design in my own project?
Its repository publishes it under the GPL-3.0 licence: you may reuse it on that licence's terms (keep the author's notice, and for a copyleft licence share your changes alike).