IWR AOP MODULE

IWR-AOP-MODULE

Revision 1.0 · KiCad 10 · six-layer, 85.6 × 33.7 mm · in production

A self-contained 60 GHz mmWave radar module built around TI's IWR6843AOP (antenna-on-package). It boots its own firmware from on-board flash and connects to a PC over USB-C or a carrier through two rear sockets.

Features

• Radar. IWR6843AOP: 60–64 GHz FMCW, 4 GHz continuous sweep, 3 transmitters and 4 receivers with antennas in the package, C674x DSP, hardware FFT/CFAR accelerator and Arm Cortex-R4F. Detection and tracking run on the radar; the host receives results.
• Standalone boot. 32 Mbit QSPI flash (U301, MX25L3233F).
• USB-C. One cable supplies power and two CP2105 serial ports: control/flashing and radar data. BOOT and RESET buttons select flashing mode.
• Carrier. 5 V input, UART and SPI, boot-mode select, reset, disable, interrupt, hardware frame-start pulse and frame-sync input.
• Power. USB-C or carrier 5 V feeds an ideal-diode OR and four-rail TI LP87524J-Q1 PMIC. The PMIC sequences the rails, holds the radar in reset until they are good, and asserts reset when the carrier disables them.
• Debug. Rear Cortex-10 JTAG header for development off a carrier (Black Magic Probe or XDS110), debug-boot solder jumper, and test pads for every rail, enable and reset. Flashing requires only USB and the BOOT/RESET buttons.
• RF-ready layout. The radar sits on the bottom edge with a notch above it, giving the 0.2 mm antenna edge gaps TI specifies. A GND pad sits under the die on both faces.

Key specifications

Full modes, rails, boot, mechanics, stackup and firmware requirements: hardware specification.

Using it

Use USB-C or a carrier, never both: they share the radar's control UART.

USB-C

Power from a USB-C port or charger offering at least 1.5 A (default USB power, no PD). USB-A-to-C cables and 500/900 mA ports can brown out during chirps. The CP2105 bridge enumerates as two COM ports:

Carrier

Power from one regulated 5 V supply (4.5–5.5 V, ≥ 1.5 A) on J400.11/.12, with USB unplugged. All logic is 3.3 V and not 5 V tolerant. A carrier can talk to the radar three ways:

Control and timing signals:

To flash from a carrier: hold J400.5 high, pulse J400.8 low, program over the control UART, release J400.5 and reset again.

Carrier rules (spec §5):

• Keep every carrier output and pull-up high-impedance until J400.8 first goes high, and while HOST_DISABLE is asserted.
• Reset only by pulling J400.8 low open-drain; never drive it high.

Pinout

Back view: J400 is on the left and J401 on the right.

Full pin directions and carrier rules: spec §5.

Mechanical

Back view, mm. Everything is symmetric about the board centrelines (℄). Sockets sit on the hole columns, centred vertically. Keep carrier metal out of the antenna aperture (spec §6).

Cost

First JLCPCB order, 5 boards (USD at €1 = $1.121, 5 October 2026):

The IWR6843AOP is about $21 of each board. Per-part prices: docs/bom-cost.csv.

Repository layout

IWR-AOP-MODULE.kicad_pro / .kicad_sch / .kicad_pcb / .kicad_dru   KiCad 10 project, design rules
IWR-AOP-MODULE.kicad_sch   Power entry, LM66200 source OR, enable, integration notes
rails.kicad_sch        LP87524J-Q1 PMIC, four radar rails, reset, test pads
aop.kicad_sch          IWR6843AOP, crystal, boot flash, straps, JTAG
interfaces.kicad_sch   USB-C, CP2105 dual UART, J400 / J401 sockets, buttons
libraries/             Project symbols, footprints and STEP 3D models (IWR-AOP-MODULE.*)
                       Sockets, JTAG header, buttons and LP87524J: LCSC/EasyEDA models fitted
                       to the pads; U200: KiCad's 4x4 QFN-24 model
docs/                  Hardware specification and BOM cost
  images/              Board renders, orbit GIF, pinout.svg and dimensions.svg
  videos/              IWR-AOP-MODULE-orbit.mp4
  3d/                  Board STEP (origin: outline top-left)
tools/
  board_svg.py         Pinout and dimension SVG generation
  render/              Blender product renders and orbit video pipeline
manufacturing/         JLCPCB package builder and output (jlcpcb/)
references/            Datasheets and JLC's sample BOM format
CHANGELOG.md           Release history
LICENSE                MIT license
build/                 Generated outputs (gitignored)

The project is self-contained: everything outside the stock KiCad 10 libraries is in libraries/.

Status

In production. Revision 1.0 is fully routed. ERC is clean; DRC reports 0 unconnected and 0 schematic-parity issues, plus 36 accepted findings (spec §7.3). The bring-up checklist is spec §9.

License

MIT — see LICENSE.