Tercio B1

Tercio B1

Brushless FOC on the Tercio bus.

A 46 × 46 mm field-oriented-control driver for gimbal, quasi-direct-drive and hobby brushless motors.
10–52 V, a 21-bit encoder on board, and the same bus, browser panel and libraries as the Tercio S1.

Rev A is designed and 100 % routed, and its firmware runs on a simulated motor. Nothing has run on real hardware yet:
every rating on this page is a design target until the bench tests confirm it.

Hardware · Firmware · Simulator · Spec vs moteus · Plan

Why

A Tercio machine can already put closed-loop steppers and an IMU on one CAN bus, set up from a browser. Some joints want a brushless motor instead: gimbals that must be smooth at a crawl, legs and arms on quasi-direct-drive actuators, anything that needs torque control rather than position alone.

Good brushless controllers exist, but each comes with its own adapter, its own tools and its own library. The Tercio B1 joins the bus you already have. It speaks Tercio protocol v2 as device class 2, appears in Tercio Control next to your S1 drivers and IMUs, and is driven from the same Python and Arduino libraries. It aims at the mjbots moteus-x1 and moteus-n1 on that ecosystem and on value: a target of $99–119.

Highlights (design targets)

Rev A board

• 46 × 46 mm, 6 layers: 2 oz outer and 1 oz inner copper, 1.6 mm, matte black ENIG, filled and capped vias in pads.
• Top: the XT30 on the left edge; three half-bridges across the lower half, each low-side FET with its Kelvin shunt; phase pads A/B/C on the bottom edge; the DRV8353RS above them with its 5 V buck; CAN-in, aux and CAN-out connectors on the edges; status LEDs.
• Bottom (faces the motor, ≤ 2.3 mm parts): the MT6835 on the shaft axis, the STM32G431 beside the gate driver, the CAN transceiver between the connectors, SWD pads and a named test point for every rail and phase.
• Numbers: 163 footprints, 1,237 tracks, 340 vias, 100 % routed. BOM: 54 lines, every part in stock at JLCPCB when checked on 2026-10-13, $26.08 per board at 10 and $22.44 at 100 (components).
• Fabrication: hardware/tools/jlc_fab.py writes the gerbers, BOM and placement file for JLCPCB assembly.

How it works

flowchart LR
    BUS["CAN FD bus<br/>Tercio protocol v2"] --- CAN["MCP2562FD"]
    CAN --- MCU["STM32G431<br/>FOC at 30 kHz"]
    ENC["MT6835<br/>21-bit encoder"] -- "SPI" --> MCU
    MCU -- "6 × PWM" --> DRV["DRV8353RS<br/>gate driver + 3 current amps"]
    DRV --> FET["3 half-bridges<br/>6 × BSC030N08NS5"]
    PWR["XT30<br/>10–52 V"] --> FET
    FET --> MOT(("Motor"))
    FET -. "1 mΩ Kelvin shunts" .-> DRV
    DRV -- "phase currents" --> MCU

• One call per PWM period. FocCore takes the ADC sample and returns the duties: Clarke and Park transforms, a d/q current controller with decoupling and latency compensation, space-vector PWM and per-tick protection. It is plain C++ with no HAL, so the same code runs on the MCU, in the unit tests and in the simulator.
• The joint. Joint runs the protocol-v2 states, the position, velocity, torque and impedance modes on the S1's trajectory planner, the regen clamp, a 1 s host deadman and temperature derating.
• Shared with the S1. The trajectory planner and the encoder tracker come from the S1 firmware; the CAN node and the wear-levelled settings will too (docs/07 §7.3), so the B1 behaves like the rest of the Tercio bus.

Simulator

The firmware above, unchanged, runs at 30 kHz in real time against a model of the motor and the board.

• The model: a dq motor with cogging and friction, dead time, a supply that cannot sink current, 12-bit current-sense codes, the encoder's noise and timing, and the gate driver's over-current latch.
• The page: pick a motor, run the calibration and see what it found next to the true values, then move the joint and watch the scope at 1 kHz, or one PWM period at a time.
• Testing: inject faults, load the shaft, or drag the rotor by hand.

cd firmware
node simulator/server.mjs             # http://127.0.0.1:8770, builds the simulator first if needed

Specifications (design targets)

The comparison with moteus-x1, n1 and r4.11 is in docs/02.

Building it

Firmware

cd firmware
~/.platformio/penv/bin/pio test -e native     # host tests on simulated motors

Hardware

python3 hardware/build.py                      # schematic → netlist check → ERC → PDF
python3 -I hardware/verify_bom.py              # every LCSC code checked live against JLCPCB

The board scripts need KiCad 10's own Python, for pcbnew:

KPY=/Applications/KiCad/KiCad.app/Contents/Frameworks/Python.framework/Versions/3.9/bin/python3
cd hardware
$KPY layout.py                                 # place, copper, route, fill, DRC, renders
$KPY tools/jlc_fab.py                          # build/jlc: gerbers, BOM, CPL for JLCPCB

The files in hardware/kicad/ are generated: change the code and regenerate rather than editing them in KiCad. The full flow, the router and the checks are in hardware/README.md.

Status and next steps

Documents

Repository layout

docs/        the plan: requirements, spec, parts, architecture, BOM, KiCad as code, firmware, bring-up, risks
data/        live part data, BOM estimate, pin map
tools/       part lookup (JLCPCB + LCSC), BOM estimate, CAN bus-time budget
hardware/
├── b1/      the Tercio B1 circuit, one module per sheet; placement, copper, routing plan, silkscreen
├── gen/     the generator: KiCad file writer, symbols, footprints, board engine, router
├── tools/   JLCPCB fabrication files, routing report, XT30 3D model
├── kicad/   the generated KiCad 10 project (open tercio-b1.kicad_pro to review)
└── lib/     IBM Plex fonts for the silkscreen (project footprints and symbols are in kicad/lib/)
firmware/
├── src/     foc/, control/, app/ (MCU and host); sim/, simulator/ (host only)
├── simulator/  Node server and web UI
└── test/    host tests

Data and tools

Re-run before any order (stock moves daily):

python3 -I tools/parts_lookup.py && python3 -I tools/parts_lookup.py tools/candidates-extra.txt && python3 -I tools/bom_estimate.py

Decision log

Decided with Kerol on 2026-10-12:

Still open:

Licence

Apache-2.0, see LICENSE.