

EC Debug
- Size
- 26 × 29 mm
- Copper layers
- 2
- Thickness
- 0.8 mm
- Parts
- 19
- Nets
- 23
- Pads
- 84
- Tracks, vias
- 93, 21
- Pours
- 1
- Routed
- Yes
- KiCad
- KiCad 8.0 (file 20240108)
- Created
- 14 Aug 2024
- Updated
- 14 Aug 2024
Overview
EC Debug is an open-source printed circuit board by jyancat, from the jyancat/EC-Debug repository on GitHub, published under the CERN-OHL-S-2.0 licence. It is a 2-layer board of 26 × 29 mm with 19 parts on 23 nets, routed with 93 tracks and 21 vias.
It is built around the CH340C, AP2112K-3.3 and GT-USB-7014F. Its parts include 4 capacitors, 4 resistors, 2 ICs and 2 connectors.
Main components
3CH340C
SOP-16-20℃~+70℃ 2Mbps 3.3V、5V 50uA 7mA Transceiver USB 2.0 SOP-16 USB Converters ROHSWCH (Nanjing Qinheng Microelectronics)USB ConvertersAP2112K-3.3
SOT253.3V 600mA CMOS Low Dropout Linear Regulator with EnableDiodes IncorporatedUncategorisedGT-USB-7014F
SMD-40℃~+85℃ 0.53mm 1 10,000 Cycles 16P 24V 5A 6.5mm Black Female Laminated board Type-C USB 2.0 SMD USB Connectors ROHSG-SwitchUSB Connectors
Parts
19| Qty | Value | Footprint | References |
|---|---|---|---|
| 4 | 5.1k | Resistor_SMD:R_0402_1005Metric | R1, R2, R3, R4 |
| 4 | TestPoint | TestPoint:TestPoint_Pad_1.5x1.5mm | TP1, TP2, TP3, TP4 |
| 2 | 100nF | Capacitor_SMD:C_0402_1005Metric | C2, C4 |
| 2 | 1uF | Capacitor_SMD:C_0402_1005Metric | C1, C3 |
| 2 | MountingHole | MountingHole:MountingHole_2.2mm_M2 | H1, H2 |
| 1 | 3V3 | TestPoint:TestPoint_Pad_D1.0mm | TP5 |
| 1 | AP2112K-3.3 | Package_TO_SOT_SMD:SOT-23-5 | U1 |
| 1 | CH340C | Package_SO:SOIC-16_3.9x9.9mm_P1.27mm | U2 |
| 1 | GT-USB-7014F | EC Debug:GT-USB-7014F | J2 |
| 1 | USB_C_Plug_USB2.0 | EC Debug:105444 | P1 |
Questions
How big is the EC Debug PCB?
It measures 26 × 29 mm and has 2 copper layers, 0.8 mm thick.
What parts does the EC Debug use?
19 parts, built around the CH340C, AP2112K-3.3 and GT-USB-7014F. The full list of its parts is on this page, with links to each part's symbol and footprint where PCBKit's library has them.
Where can I download the EC Debug KiCad files?
From the jyancat/EC-Debug repository on GitHub, at the commit this page was made from: the board is Hardware/EC Debug.kicad_pcb and its schematic Hardware/EC Debug.kicad_sch. PCBKit opens the board in the browser, with nothing to install.
Can I use the EC Debug design in my own project?
Its repository publishes it under the CERN-OHL-S-2.0 licence: you may reuse it on that licence's terms (keep the author's notice, and for a copyleft licence share your changes alike).
Similar boards
- 2 layers192.4 × 50 mm

- 2 layers87.5 × 77.5 mm

Panel
jpconstantineau/NRF52-Board
This Repository is a collection of NRF5x boards.
143 parts100BSD-3-Clause - 2 layers26 × 30 mm

USB C to UART
jyancat/UART-Expansion-Card
Design files for the UART expansion card, please note this is a tested and working expansion card. Licensed under CERN-OHL-S-2.0. Uses the CH340C with switchable power and logic levels (5V and 3V3)
16 parts23 - 4 layers20.3 × 40 mm

- 4 layers121.9 × 115.8 mm

SparkFun GNSS UM980 panelized
sparkfun/SparkFun_UM980_Triband_GNSS_RTK_Breakout
Documentation and hardware repository for the SparkFun Triband GNSS RTK Breakout, featuring the UM980 high precision GNSS/RTK module from Unicore Communications
584 parts11 - 2 layers65 × 100 mm

Syringe pump
wenzel-lab/syringe-pumps-and-controller
Design of 3d printable syringe pumps and dual controller.
141 parts11 - 2 layers52.9 × 22.9 mm

MSP430G2553-Feather
upsidedownlabs/MSP430G2553-Feather
MSP430G2553 based Adafruit feather compatible board 🪶
76 parts10 - 2 layers30 × 60 mm
