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2 layers72.5 × 40 mm0bCLK, the printed circuit board in 3D

11 LED Binary Clock using an ATmega48A

Size
72.5 × 40 mm
Copper layers
2
Thickness
1.6 mm
Parts
18
Nets
25
Pads
66
Tracks, vias
74, 6
Pours
2
Routed
Yes
KiCad
KiCad 7 (file 20221018)
Created
16 Nov 2024
Updated
1 Jul 2025

Overview

0bCLK is an open-source printed circuit board by Jvlse, from the Jvlse/0bCLK repository on GitHub. It is a 2-layer board of 72.5 × 40 mm with 18 parts on 25 nets, routed with 74 tracks and 6 vias.

It is built around the ATMEGA48A-PU. Its parts include 11 diodes, 3 switches, 1 IC, 1 connector and 1 crystal. It belongs with the AVR (ATmega, ATtiny) boards of this library.

Main components

1

README

README.md

0bCLK

11 LED Binary Clock using an ATmega48A, Datasheet

Code is here

FEATURES:

  • Binary Time on 11 LED's with PWM brightnesscontrol
  • Control over buttons
  • Sleepmode with shown reduce of power
  • Timebase using Timer and quartz crystal (accuracy can be messured at PB0)
  • Flashing using ISP, for example using a USBasp and avrdude or an Arduino

Schematic:

Alt text

PCB:

  • I used a mill for the 2-layer PCB
  • All components are mounted on the top and soldered on the bottom
  • I used CR2032 battery cells
  • For orientation of the ISP:
    • the square pad on the footprint is the VCC pin of the 6-pin ISP

Alt text

Command for flashing using avrdude in Windows:

avrdude -c [programmer] -p m48A -Uflash:w:Path\To\CLK\Debug\CLK.hex:i

Example using USBasp, path is "C:\Atmel_Studio\7.0\CLK\Debug\CLK.hex":

avrdude -c usbasp -p m48A -Uflash:w:C:\Atmel_Studio\7.0\CLK\Debug\CLK.hex:i

Power saving:

  • If CPU is doing nothing (waiting for Timer interrupt)
    • goes to PWR_SAVE (basically completely off exept async Timer and interrupt)
  • Disabling individual Timers, Two Wire Interface (TWI), Universal Synchronous Asynchronous Receiver Transmitter (USART0) and Analog Digital Converter (ADC)
  • more optimizations: turning off Watchdog timer, brown out, lower CPU CLK, lower voltage, using sleepmodes

Fuse bits:

  • SPIEN: LEAVE ON!
    • else it won't be flashable using SPI/ISP anymore
  • WDTON: OFF
    • Watchdog timer not needed
  • CKDIV8: OFF
    • no system clock division needed
  • BODLEVEL: Maybe
    • if left off a brown out might lead to malfunction

Power usage:

  • Default 6,5mA -> 35h runtime
  • PWR_SAVE 1,2µA -> 191666h ~ 20 years runtime

CLK inaccuracy:

  • Reasons:
    • No Capacitors at quartz crystal, quartz temperature (25°C is optimal)
  • Messuring:
    • Output of Pulse Per Second (PPS) Signal at PB0 and meassuring using a counter

Timers:

  • Timer 0: every ms for PWM
  • Timer 2: every second for timebase

Buttons:

  • PD0 -> down (PCINT16/RXD)
  • PD1 -> up (PCINT17/TXD)
  • PD2 -> mode (PCINT18/INT0)

Ports:

  • Data Direction Register:
    • DDR=0: Pin is input (button)
    • DDR=1: Pin is output (LED)
  • PORT-Register:
    • if DDR=0
      • 1: Pull-up resistor is active, for button
      • 0: Pull-up not active
    • if DDR=1
      • 1: High voltage output
      • 0: Low voltage output

Parts

18
QtyValueFootprintReferences
11LEDLED_THT:LED_D3.0mmD1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11
3SW_PushButton_Switch_THT:SW_PUSH_1P1T_6x3.5mm_H5.0_APEM_MJTP1250SW1, SW2, SW3
1ATmega48A-PPackage_DIP:DIP-28_W7.62mmU1
1Battery_CellBattery:BatteryHolder_Keystone_106_1x20mmBT1
1Conn_02x03Connector_PinSocket_2.54mm:PinSocket_2x03_P2.54mm_VerticalJ1
1Quartz CrystalInductor_THT:L_Radial_D6.0mm_P4.00mmY1

Questions

How big is the 0bCLK PCB?

It measures 72.5 × 40 mm and has 2 copper layers, 1.6 mm thick.

What parts does the 0bCLK use?

18 parts, built around the ATMEGA48A-PU. The full list of its parts is on this page, with links to each part's symbol and footprint where PCBKit's library has them.

Where can I download the 0bCLK KiCad files?

From the Jvlse/0bCLK repository on GitHub, at the commit this page was made from: the board is KiCad/KiCad.kicad_pcb and its schematic KiCad/KiCad.kicad_sch. PCBKit opens the board in the browser, with nothing to install.

Can I use the 0bCLK design in my own project?

Its repository states no licence, so its author keeps all rights: ask Jvlse before reusing the design.

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