TK2000 VDPboard

TK2000 VDP Board

DISCLAIMER

Any use of this project is under your own responsibility. You will be responsible of checking the correct construction and functionality of your board. By using this project You will agree that I cannot be held responsible if it will destroy any of your devices, damage your computer, burn down your house or whatever.

Sponsorship

This project is kindly sponsored by PCBWay. PCBWay specializes in manufacturing high-quality PCBs and makes them affordable to hobbyist and professionals alike.

The range of services they offer include PCB prototyping, assembly, instant quotes for your order, a verification process by a team of experts and an easy to use, hassle-free order process.

I'm grateful to PCBWay for the help in evolving and testing this project. You can order the currently released revisions of the board from them, see the link below!

Introduction

The VDP board adds a TMS9918A Video Display Processor to the TK2000 computer, featuring colors, sprites and fascinatingly low resolution!

This board is meant to be used in the TK2000 bus extender and is part of my project to build a set of cards for the TK2000 computer.

You can build yourself a TK2000 computer using files from this repo and following my build notes.

Support

If you wish to support me in building new hardware and software for old machines, throw a few euros in my direction via Ko-Fi ☕!

Hardware

The board was designed with KiCad EDA.

Bill of Materials

Notes

I found about this the hard way: the VDP internal state machine gets tripped by the dummy reads the 6502 generates while performing absolute + indexed access, so, unless you want to suffer, use absolute addressing to access the memory mapped ports on this board.

Configuring the address

The address for the I/O ports can be changed by jumpering the VIA 1/VIA 2 headers to the middle row.

      C C C C C C C C
      0 0 0 0 0 0 0 0
      8 9 A B C D E F
	  x x x x x x x x
 J1   . . . . | . . .
      . . . . | . . .
              ^ default
			  
JP1 is set by default with 1-2 closed (/IRQ)
JP2 is closed by default (/RES is connected)			  

The port at 0xC0x0 will be the memory port (MODE pin set at 0), while the 0xC0x1 port will access the registers.

Ordering the boards

You can order the board for this project at PCBWay and support me or download the gerbers and have them printed wherever you like!!!

Fixes

Rev. 0

It is advisable to install a 470pF or similar capacitor between pins 7 and 9 of U3. This adds a delay to the /CS from the '138 decoder, avoiding the generation of a spurious spike on the /CSR signal, caused by propagation delay in U3.

Rev. 1 has space for the capacitor directly on the PCB.