OPEN PHASE

OPEN_PHASE – PHASETRACKER

3-phase inline current and voltage sensing PCB for BLDC drone motors (INA241A2 + AD7606C-18)

Sub-project of OPEN THRUST LAB

_{Full-resolution video: Images/OPEN_PHASE.mp4 (KiCad raytracing, kicad-cli pcb render)}

OVERVIEW

OPEN_PHASE is an open-hardware measurement board developed as part of OPEN THRUST LAB, a community-driven project building open-source test benches for drone motor characterization.

The board is inserted between the ESC and a 3-phase BLDC motor (two Amass MR60PW connectors) and between the battery and the ESC (two Amass XT60PW connectors). On each motor phase (U, V, W) and on the battery line (B) it measures:

• the current, with a 1 mΩ four-terminal shunt (Isabellenhütte PBV-R001) and a TI INA241A2 current-sense amplifier (20 V/V, enhanced PWM rejection, bidirectional around a 2.5 V reference);
• the voltage, with a 40.2 kΩ / 10 kΩ divider.

The eight signals are sampled simultaneously by an Analog Devices AD7606C-18 (8 channels, 18 bits, 1 MSPS), so that power, efficiency and ESC behaviour can be computed from time-aligned Vu/Vv/Vw, Iu/Iv/Iw and the battery voltage and current Vb/Ib.

The board only needs 3.3 V. An LT8362 boost converter (2 MHz) makes 6 V, and two LT3045-1 ultralow-noise LDOs make the analog rails. Each LDO has its SET pin driven by an LTC6655 precision reference, so the LDO works as a low-noise buffer for the reference: +5VA (ADC and amplifier supply) and +2.5VA (ADC reference and amplifier zero-current level).

This project was first published as PhaseSense-8586, after the first version of the design (INA240 + ADS8586S). The schematic now uses the INA241A2 and the AD7606C-18; everything in this README is taken from the current netlist.

STATUS

This revision is not ready for fabrication. What is in the repository today:

See DESIGN REVIEW for the points found while documenting and simulating the design.

SPECIFICATIONS

Electrical specifications

ADC channel assignment

The four channels are numbered alike: Rn = 33 Ω and Rn+1 = 9.1 kΩ (current filter), Rn+2 / Rn+3 = divider, Rn+4 = 9.1 kΩ (voltage filter), with n = 15 (U), 20 (V), 25 (W), 30 (B). Re1 … Re4 are the 1 kΩ series resistors of the voltage filters.

Current sign: IN+ of each INA241 is on the output side of the shunt (J2 for the phases, J5 for the battery), so a current flowing from J1 to J2, or from J3 to J5, lowers the output: V = 2.5 V − 20 mV/A × I(J1→J2). The voltage is measured on the same output side of the shunt.

Power budget

Power chain: +3.3 V (host) → LT8362 → +6 V → LTC6655 + LT3045-1 → +5VA / +2.5VA

Physical specifications

SCHEMATIC ARCHITECTURE

Five functional hierarchical sheets (under Project Architecture), plus the documentation sheets (Block Diagram, Power - Sequencing, Revision History):

DESIGN REVIEW

Points found while checking the documentation against the netlist and the datasheets, and while simulating the design. Unless marked Fixed, none of them has been changed in the schematic: they are design decisions to take.

Two findings on the +2.5VA rail have been fixed.

IC3 was an LTC6655LN-2.5 wired like the standard part, with pin 6 tied to pin 7. On the LN version pin 6 is NR (noise reduction, to be decoupled to ground), not VOUT_S. IC3 is now a standard LTC6655-2.5 on the same footprint, for which this wiring is correct. The LTspice model of the LN part does not model the NR pin, so it could not show what the old connection did.

R12, on the SET pin of IC9, was 49.9 kΩ. The LT3045-1 sources 100 µA from SET, so the pin wanted 4.99 V against the 2.5 V reference and +2.5VA settled at 2.549 V, outside the 2.495 – 2.505 V reference window of the AD7606C. R12 is now 24.9 kΩ (100 µA × 24.9 kΩ = 2.49 V): +2.5VA settles at 2.4996 V.

SIMULATION (LTspice)

The power chain and the two measurement channels are simulated with LTspice 26 in Simulation/LTspice/. Every component value comes from the KiCad netlist and keeps its reference designator, so the simulation schematics can be read side by side with the KiCad sheets.

Models

• LT8362, LT3045-1, LTC6655-5, LTC6655-2.5: official Analog Devices models shipped with LTspice.
• INA241A2: TI does not provide an LTspice model, so INA241A2_behav.sub / .asy is a behavioral model written for this project from the datasheet (SBOSA30D): gain 20 V/V around (REF1 + REF2) / 2, 1.1 MHz bandwidth, 8 V/µs slew rate, output swing, 2.5 mA supply current, 35 µA input bias. Gain and input offset are parameters, nominal except in simulation 08. It does not model noise, CMRR or the 1 µs output hold of the enhanced PWM rejection.
• AD7606C-18: loads only. AVCC and VDRIVE are current sources (45 mA and 1.8 mA, the 1 MSPS figures). Each analog input is 1.2 MΩ to an internal 2 V node plus 5 pF, from the datasheet ("Analog Input Current = (VIN − 2)/RIN").
• D2: PMEG2020EH modelled with the LTspice PMEG2020AEA (same 20 V / 2 A Nexperia MEGA Schottky family). L1: 2.2 µH, 22 mΩ (Würth WE-MAPI 4030, 74438357022).
• Ceramic capacitors use their nominal value (no DC-bias derating).

Results

Re-run the simulations (Windows, LTspice installed in the default location):

cd Simulation/LTspice
python run_simulations.py            # runs LTspice in batch mode, redraws Images/Simulation/*.png, results.md and measurement_quality.md
python run_simulations.py --no-run   # only redraw from the existing .raw files
python generate_asc.py               # rebuilds the .asc files (overwrites hand edits)

Or open any .asc in LTspice and press Run. Simulation 01 switches at 2 MHz for 12 ms and takes about 7 minutes; 03 takes about 2 minutes.

The simulations validate the design intent (regulation, sequencing, filtering). They do not replace bench measurements: layout parasitics, capacitor DC-bias derating and the real PWM edges on the phases will change the figures. The steady-state ripple is simulated on the boost alone because the encrypted LDO and reference models cannot be started from a preset operating point; what is left on the analog rails is computed from the simulated PSRR.

MEASUREMENT QUALITY (predicted)

Simulations 07 and 08 estimate how good the measurements will be before a board is built. run_simulations.py compares the readings with the simulated truth, adds what the datasheets say about the parts that are not simulated, and writes the full report to Simulation/LTspice/measurement_quality.md.

How far a reading is from the truth (one reading of a steady value)

• No calibration: the firmware uses the schematic values. The current reads about 0.75 A too high (15 mV offset of the current channel, DESIGN REVIEW 5) and the voltage about 0.7 % too low. The interval holds 95 % of the boards.
• Zero taken before the run: the reading at 0 A is subtracted. What is left on the current is the ±0.5 % tolerance of the shunt.
• Zero and gain calibrated: the gain has been calibrated once against a known current and voltage. What is left is the drift 20 K away from that calibration, shunt self-heating included (datasheet maxima added together).
• Noise of one sample: 10 mA rms and 0.85 mV rms (1 LSB = 3.8 mA and 0.39 mV). It averages out.

Under PWM (simulation 07: 25.2 V battery, 24 kHz PWM, motor phase of 30 µH / 50 mΩ, 20 A peak at 1 kHz, 90 W in the phase)

Shunt R1 / R4 / R7 / R9 (PBV-R001-F1-0.5, Isabellenhütte datasheet): tolerance ±0.5 %, temperature coefficient below 75 ppm/K, thermal resistance below 15 K/W (1.2 W and +18 K at 35 A, for 3 W allowed), inductance below 10 nH, thermal EMF below 2 µV/K (2 mA of offset per kelvin of difference between the two sense terminals). The other resistors have no part number in the schematic: 1 % and 100 ppm/K are assumed for them.

Method

• 07, dynamic accuracy. The simulated phase voltage and motor current are the truth. The readings are rebuilt from the AD7606C pin voltages as a firmware would do it. Three runs: shunt without inductance, with 5 nH, with 10 nH.
• 08, static accuracy. Monte Carlo on 1000 boards: shunt 0.5 %, resistors 1 %, INA241A2 gain ±0.01 % and offset ±15 µV, AD7606C input resistance 1.0 – 1.4 MΩ, +2.5VA built from the LTC6655B tolerance, the SET network and the LT3045-1 offset (2.4949 … 2.5046 V over the 1000 boards, 0.1 % of them outside the 2.495 – 2.505 V reference window of the AD7606C).
• ADC. The AD7606C-18 is not simulated. Its datasheet figures are applied to the simulated pin voltages: ±10 V range, 25 kHz input filter (low bandwidth mode), SNR 92.5 dB, full-scale error ±120 LSB, zero error ±80 LSB.

Not covered: the common-mode rejection of the INA241A2 and its 1 µs output hold at each PWM edge (behavioural model), the layout, and the other two phases (the waveform is a single-phase equivalent). The PWM figures are for this test waveform; change the .param line of simulation 07 for another motor or another PWM frequency.

STARTUP SEQUENCE

After 3.3 V is applied (values from the LTspice simulations):

The LT3045-1 Power-Good outputs are not used (PGFB tied to IN), so there is no hardware "rails ready" signal: use the delay.

HOW TO USE

Prerequisites

• KiCad 10 (files are saved in KiCad 10 format and cannot be opened with KiCad 9 or earlier)
• Nothing else: every symbol, footprint and 3D model is in lib/ and referenced relative to the project (KIPRJMOD, project-local sym-lib-table / fp-lib-table)
• KiBot for automated output generation, Docker recommended for local CI runs

Generate outputs locally

./kibot_launch.sh               # default configuration
./kibot_launch.sh -v CHECKED    # specific variant

REPOSITORY CONTENT

DIRECTORY STRUCTURE

.
├─ Computations       # Design notes and calculations
├─ HTML               # Generated HTML pages
├─ Images             # Pictures, renders
│  └─ Simulation      # Figures drawn by Simulation/LTspice/run_simulations.py
│
├─ kibot_resources    # External resources used by KiBot
│  ├─ colors          # Color themes for KiCad outputs
│  ├─ fonts           # Fonts used in generated documents
│  ├─ scripts         # Helper scripts used with KiBot
│  └─ templates       # Templates for KiBot reports (this README: readme.txt)
│
├─ kibot_yaml         # KiBot YAML configuration files
├─ KiRI               # KiRI PCB diff viewer files
│
├─ lib                # Project libraries (self-contained)
│  ├─ lib_sym         # OPEN_PHASE.kicad_sym — every symbol used
│  ├─ lib_fp          # OPEN_PHASE.pretty — every footprint used
│  └─ 3d_models       # STEP models referenced by the footprints
│
├─ Logos              # Project logos
│
├─ Manufacturing
│  ├─ Assembly        # BoM, position files, assembly notes

DEVELOPMENT WORKFLOW

This project uses a reproducible hardware workflow based on KiCad 10, KiBot and GitHub Actions.

The CI pipeline (.github/workflows/ci.yaml) runs KiBot on every push to dev or main and commits the generated outputs back ("Update Outputs" commits). Always git pull after the CI has run, before editing the project again, otherwise the regenerated files (.kicad_pro, BoM, netlist, README…) will conflict.

ℹ️ README.md is generated by KiBot from kibot_resources/templates/readme.txt. Edit the template, not README.md, or your changes will be overwritten by the next CI run.

Branch convention: dev is the development branch; main only receives merges from dev and carries the release tags.

Project metadata (project name, board name, company, designer, logo, repository URL) is defined once in kibot_yaml/kibot_main.yaml (definitions: section) and propagated to title blocks, documents and this README.

Release a new hardware revision:

1. On dev, fill the [Unreleased] section of CHANGELOG.md.
2. Switch kibot_variant to CHECKED in ci.yaml once ERC and DRC are clean.
3. Merge dev into main: git checkout main && git pull && git merge dev && git push
4. Tag with a plain semantic version (no v prefix): git tag 1.0.0 && git push origin 1.0.0
5. Re-sync dev: git checkout dev && git merge main

CHANGELOG

See CHANGELOG.md (Keep a Changelog format, semantic versioning).

LICENSE

The hardware design files in this repository are released under the CERN Open Hardware Licence Version 2 – Permissive (CERN-OHL-P v2). See LICENSE for the full licence text.

Copyright 2026 Dimitry Siebert, OPEN THRUST LAB. Source location: https://github.com/foukouda/OPEN_PHASE.

Under CERN-OHL-P v2:

• You may use, study, modify and manufacture this design freely
• Derivative works do not need to remain open source
• Modified files must carry a notice stating that they were modified, with the date and a short description of the changes
• The original copyright and licence notices must be preserved
• The design is provided "as is", without any warranty (section 5 of the licence)

The KiBot configuration and CI workflow come from the KDT_Hierarchical_KiBot template by Nguyen Vincent (MIT licence).

For more on CERN-OHL licences: cern-ohl.web.cern.ch