SN-64

SN 64 KiCad schematic draft

Open sn64.kicad_pro in KiCad 10, then open the schematic. The root (rev 0.4-r3, A2) holds both cartridge connectors and five child sheets, wired by same-name root labels (the shared net-name contract in system-integration.md):

• page 2: the USB programmer child sheet (exports USB_VBUS, USB_3V3, USB_CC1/CC2, jtag_tck/tms/tdi/tdo, TARGET_VREF; R101/R102 DNP because the power sheet's TUSB320 presents Rd);
• page 3: the SNES cartridge interface child sheet (rev 0.3.1-cart: 5 V/3.3 V translators, reset/IRQ/CIC paths, per-pin CIC data translators; see notes);
• page 4: the FPGA child sheet (rev 0.5-fpga, no HDMI pins, designators 4xx: LFE5U-85F CABGA381 with all 381 balls assigned, W25Q128JVSIQ configuration flash, JTAG, SN74CB3Q3384A N64 bus switches; see notes). Its pin table also generates interfaces/fpga-pin-map.csv and fpga/constraints/sn64_board.lpf;
• page 5: the power child sheet (designators 3xx: host/USB eFuse priority mux, TUSB320, TPS63070 5V_PRE, three TLV62569 FPGA rails, default-off cartridge eFuse and interface switch, monitors; see notes);
• page 6: the clock/cartridge-audio child sheet (draft 0.2-av, designators 7xx: Si5351A + 25 MHz crystal, 25 MHz FPGA oscillator, PCM1808 I2S-master cartridge-audio ADC; the HDMI output of draft 0.1-av was removed on 2026-09-29; see notes).

The PDF is a review export of all six pages; the round-3 export was not visually inspected (no rasteriser available). Project-local libraries hold the symbols KiCad does not ship. It is not a complete electrical design or a manufacturing package.

The SNES socket now lives on its own small board: ../sn64-socket/ (generated by tools/split_socket_board.py; design note mechanical-architecture.md). On this main board, J2 is the 2x40 2.00 mm joint header. Check both boards with tools/verify_socket_joint.py (and --negative-test).

Board (first draft, 2026-09-29): sn64.kicad_pcb is generated by tools/build_main_pcb.py: 6 layers, 1.2 mm, PCBWay-compatible rules, the SummerCart64 lower outline extended to 70 mm above the tongue shoulders, all 410 parts imported with their 530 nets and a connectivity-pulled placement inside block zones (N64 interface at the bottom, FPGA centred with its decoupling underneath, translators under the top joint header with their resistor arrays beneath them, power/USB left, clock/audio right; small passives on the bottom side). DRC after placement (rebuilt 2026-09-29 without the HDMI parts): 0 real errors; the only reports are the USB-C receptacle pads at the board edge (by design; rule exception in sn64.kicad_dru) and the N64 fingers' shared solder-mask opening (SummerCart64 footprint).

Routing draft (2026-09-30): the tracked board now carries a first autorouted draft (notes): FPGA rotated 180° so its N64 bank faces the bus switches, 240 dog-bone fan-out vias, GND plane on In1, 3.3 V plane on In3, 1.1 V island on In4, signals routed by KiCadRoutingTools (Rust A*, run 2), 157 plane vias, outer GND pours. DRC: no shorts, crossings, clearance or hole violations. Still open: 75 signal/power nets (95 connections, mostly in the translator row) and 219 plane pads without a via (validation/pcb-open-connections.json). Tools: tools/prepare_route.py, tools/add_plane_vias.py, tools/finish_route.py, tools/fab-pcbway.txt. Rerunning build_main_pcb.py --force regenerates the placement and discards this routing. Renders: top, bottom. Nothing is routed yet; the placement is a starting point, not a reviewed layout.

What is present

GND is the only net that directly crosses the USB/host-connector boundary. HOST_3V3, HOST_12V, SNES_5V_CART, USB_VBUS, USB_3V3 and TARGET_VREF are distinct nets. USB_VBUS also feeds the power sheet's default-off USB input (U302, enabled only when the TUSB320 U301 reports at least 1.5 A and USB_3V3 is present); TARGET_VREF comes from FPGA_3V3 through R414 on the FPGA sheet and is not a USB target-power output. The N64 edge reaches the FPGA only through the host-gated bus switches; N64_AUDIO_L/R and the reserved edge contacts stay unconnected. _N in net names denotes active low; the cartridge symbols retain the source maps' slash notation.

Connector pins deliberately have the ordinary passive connector type. The CSV and electrical notes, rather than these pin types, define endpoint direction and special handling. ERC cannot establish drive ownership, voltage tolerance or timing at these pending interfaces.

The USB bridge uses MPSSE JTAG with ACBUS6 controlling the translator's pulled-up, default-disabled /OE. The documented host command must include --status-pin 14. Its target JTAG nets now reach the ECP5's dedicated JTAG balls on the FPGA sheet (round 3); the configuration flash is loaded through the FPGA. The programming architecture records blank-EEPROM startup, power isolation, persistent-loading requirements and the remaining tests. Connector and crystal notes record the source geometry and provisional 11 pF crystal load capacitors.

Reused geometry and its limits

The SNES footprint retains all 62 pads, 2.5 mm ordinary pitch, two 7.5 mm gaps per row, 5 mm row separation, 1.524 mm pads and 0.762 mm drills. A specific purchasable socket, body dimensions and mounting details still need approval before board layout.

The N64 footprint preserves all 50 source pads, 2.5 mm pitch and 1.5 x 7 mm copper dimensions. Pads 1-25 remain on B.Cu and 26-50 on F.Cu. Its origin corresponds to source board coordinates (150,125), so pads are at local Y=6 mm. Six retained Edge.Cuts segments form the open lower connector profile, ending at local (±32.25,0) with its bottom at Y=10.5 mm. Do not duplicate these cuts when extending the board outline. The footprint does not include a complete board perimeter, mounting holes, layer stack or bevel. Those are separate controlled dimensions in the geometry record. No generic KiCad board thickness should be treated as the connector thickness.

See THIRD_PARTY.md, cartridge provenance and USB provenance for sources, modifications and retained licenses. All 24 USB footprint pad objects also match the source geometry in the footprint review. The copies of upstream footprints are reference assets, not a fit-tested SN 64 board.

Validation and reproducibility

KiCad 10.0.6 exports the six-page schematic to XML and PDF. The round-3 PDF was not visually inspected (no rasteriser on this machine); earlier two-sheet exports were. The saved ERC report contains zero errors and 10 warnings: 5 isolated_pin_label on the reserved N64 edge labels (N64_AUDIO_L/R, N64_KEY1/KEY2_RESERVED, N64_VIDEO_SYNC_RESERVED) and 5 pin_to_pin (cartridge U206 unused B4-B8 on the flagged GND). On the integrated root: verify_cart_interface.py 20/20 (negative 6/6), verify_power_sheet.py 23/23 (negative 11/11), verify_av_clock_sheet.py 30/30 (negative 12/12), verify_fpga_sheet.py 12/13 (negative 10/10; the failing check is efuse_fault_n, a 5V_PRE divider on ball K4, an open owner decision in system-integration.md), verify_root_connectivity.py 4/4 (negative 4/4). The schematic is incomplete and is not an ERC-clean release. Rerun checks as circuitry changes.

The independent validation script checks the exported connector pin/net assignments against the separately researched maps, rejects accidental cross-domain connections, and compares both footprints against the original downloaded sources. The corresponding result and review record the result and remaining limitations.

The saved reports record 30 cartridge-interface checks passed and 69 USB checks passed, with zero failed checks (the USB set now also checks the DNP CC resistors and the CC/VBUS/USB_3V3/JTAG/TARGET_VREF exports). The USB validator independently exports the schematic and compares it with fixed manufacturer pin tables, checking all USB component pins, rail separation, CC/data/ESD connections, bridge support, JTAG directions and disabled startup. See its result and review. These are static checks; no USB enumeration, clock measurement, suspend-current measurement, programming, cold boot, electrical protection or compatibility test has been performed on SN 64 hardware.

To regenerate review files after editing, run these from this directory with KiCad's CLI on PATH:

kicad-cli sch export netlist --format kicadxml -o validation/sn64.xml sn64.kicad_sch
kicad-cli sch export pdf -o exports/sn64-interface-draft.pdf sn64.kicad_sch
kicad-cli sch erc --format json --output validation/erc.json --exit-code-violations sn64.kicad_sch

The per-sheet and root checks, from the repository root with KiCad's Python (each also takes --negative-test, except the interface and USB validators):

$py = 'C:\Program Files\KiCad\10.0\bin\python.exe'; $cli = 'C:\Program Files\KiCad\10.0\bin\kicad-cli.exe'
& $py hardware/sn64/tools/verify_interfaces.py --source-root . --kicad-cli $cli
& $py hardware/sn64/tools/verify_usb_programmer.py --kicad-cli $cli
& $py hardware/sn64/tools/verify_cart_interface.py --kicad-cli $cli
& $py hardware/sn64/tools/verify_fpga_sheet.py --kicad-cli $cli --lattice-csv <ECP5U-85 pinout CSV> --datasheets <dir>
& $py hardware/sn64/tools/verify_power_sheet.py --kicad-cli $cli
& $py hardware/sn64/tools/verify_av_clock_sheet.py --project hardware/sn64 --kicad-cli $cli
& $py hardware/sn64/tools/verify_root_connectivity.py --kicad-cli $cli

The initial authoring script, create_interface_draft.py, uses KiCad's Python and downloaded upstream sources. It refuses to replace an existing schematic unless explicitly passed --force. Once circuit editing begins, edit the native KiCad files; do not regenerate the initial sheet over the circuit work.

add_usb_programmer.py records how the initial USB sheet was authored from the reference designs and installed KiCad libraries. It also refuses to replace its sheet without --force; use native KiCad editing for subsequent development. Regeneration requires --source-root <original-project-with-downloads> and --kicad-share <KiCad-share-directory>, and intentionally replaces the entire USB child sheet when forced.

Remaining integration

Required in the first revision: a side-mounted USB-C data/programming port and matching enclosure opening, supporting initial firmware/FPGA loading, updates and recovery without successful host-console boot. The bridge and service-access circuit now exists; the complete programming path remains pending target integration and testing. Final side-port placement, cable access and shell clearances remain mechanical work.

1. Build the power budget for the FPGA, memory, digital A/V and real cartridges on both hosts. The M64 reference annotates a 500 mA cartridge limiter; that is not a guaranteed SN 64 allowance. There is no 5 V N64 edge supply. Select input power, no-backfeed paths and default-off protected cartridge power from the actual budget.
2. Adapt the sd2snes translator circuit using the reuse review. Reverse address/strobe ownership for a console endpoint; define enable, read/write turnaround and power-off behavior for the exact part. Separately implement IRQ/reset, CIC, expansion and analog audio.
3. Integrate the reusable SNES FPGA core, physical cartridge bridge and N64 endpoint. Select FPGA/package and memory only after resource, I/O, clock and timing evidence. Connect the USB programmer to the selected target and persistent configuration storage, define programming power/boot straps and package the loading/recovery software. Add health monitoring and A/V, then review the complete schematic.
4. Place and route a PCB with the verified mechanical constraints; develop the FreeCAD enclosure around that assembly. Produce PCBWay files after electrical review and prototype/fit validation.

These are stages of the full specification. PAL, protection, save integrity, telemetry, factory testing and all remaining specification targets are retained. Video and audio go to the console over the cartridge bus (console video path); the adapter has no output of its own. No PCB layout, FPGA bitstream, working adapter, print-ready shell or PCBWay manufacturing release is included in this revision.