2 layers240 × 47 mm
2 layers240 × 47 mm
Layouts
djmango/lightbar-dock1power distribution board
- Size
- 240 × 47 mm
- Copper layers
- 2
- Thickness
- 1.6 mm
- Parts
- 129
- Nets
- 108
- Pads
- 451
- Tracks, vias
- 6,254, 240
- Pours
- 1
- Routed
- Yes
- KiCad
- KiCad 10.0 (file 20260206)
- Created
- 4 Jul 2026
- Updated
- 29 Jul 2026
Overview
Layouts is an open-source printed circuit board by djmango, from the djmango/lightbar-dock repository on GitHub, published under the MIT licence. It is a 2-layer board of 240 × 47 mm with 129 parts on 108 nets, routed with 6,254 tracks and 240 vias.
Its parts include 52 resistors, 31 capacitors, 14 diodes, 8 fuses and 5 ICs.
README
ci/artifacts/README.mdPinned manufacturing + route inputs
| File | Role |
|---|---|
v3-manufacturing.kicad_pcb / .kicad_pro | Fab golden — CI DRC + pcbkit pin |
manifest.toml | sha256 pins for the fab golden |
v3-for-route.kicad_pcb / .dsn / .kicad_pro | Unrouted board + Specctra DSN for board:make |
fp-lib-table | Resolves tscircuit:* footprints for KiCad lib checks |
Silk / lib hygiene helpers (after footprint edits):
bun run fix:silk # drop USB/SS54 F.SilkS shell lines that clip pads/edge
bun run fix:fp-lib # strip shared-package Supplier PN + normalize property atsDRC gates enforce silk_edge_clearance=0, silk_over_copper=0, and
lib_footprint_issues=0. lib_footprint_mismatch (shared-package metadata
drift) is not gated — use KiCad “Update Footprints from Library” carefully
if you need a clean mismatch count; do not rewrite embeds with ad-hoc scripts.
Placement → for-route → DSN refresh
When placement / netlist / pads change:
bun run export:kicad # → generated/kicad/v3-unrouted.kicad_pcb
bun run for-route:promote # copy into ci/artifacts + export DSN (Docker kicad)
# or, if Docker/pcbnew unavailable:
# 1. copy/promote PCB+pro into ci/artifacts/v3-for-route.*
# 2. KiCad GUI: File → Export → Specctra DSN
# 3. bun run dsn:check
bun run board:make -- --pin # Freerouting → zone fill → DRC → refresh fab pinRouting copper changes alone do not require a new DSN — only footprint moves / pad / netlist changes do.
bun run dsn:check (also part of verify:ci) fails if DSN placement drifts from v3-for-route.kicad_pcb.
Refresh fab pin after a green board:make
bun run board:make -- --pin # local, with Docker or kicad-cli
# or copy workflow artifact board-make-filled → generated/kicad + update manifestCI also runs board:make on a schedule and when route inputs / pcbkit-route change
(see .github/workflows/board-make.yml). Fast PR CI still gates the pinned
manufacturing board in build.yml.
Parts
129| Qty | Value | Footprint | References |
|---|---|---|---|
| 16 | 22kΩ ±1% | UNI_ROYAL_0402WGF2202TCE:R0402 | R20, R21, R24, R25, R28, R29, R32, R33, R36, R37, R40, R41, R44, R45, R48, R49 |
| 16 | 22µF ±20% | Samsung_Electro_Mechanics_CL21A226MAQNNNE:C0805 | C9, C10, C11, C12, C19, C20, C21, C22, C24, C25, C26, C27, C28, C29, C30, C31 |
| 9 | 1kΩ ±1% | UNI_ROYAL_0402WGF1001TCE:R0402 | R19, R22, R26, R30, R34, R38, R42, R46, R50 |
| 8 | Jing_Extension_of_the_Electronic_Co_918_118A2021Y40006:USB-C-SMD_918-118A2021Y40006 | USB2, USB3, USB4, USB5, USB6, USB7, USB8, USB9 | |
| 8 | BHFUSE_BSMD1812_150_33V:F1812 | F1, F2, F3, F4, F5, F6, F7, F8 | |
| 8 | Hubei_KENTO_Elec_KT_0603G:LED0603-RD | LED2, LED3, LED4, LED5, LED6, LED7, LED8, LED9 | |
| 8 | 100mΩ ±1% | UNI_ROYAL_1206W4F100LT5E:R1206 | R23, R27, R31, R35, R39, R43, R47, R51 |
| 7 | MountingHole_M3 | H1, H2, H3, H4, H5, H6, H7 | |
| 6 | 10µF ±10% | Murata_Electronics_GRM21BR61H106KE43L:C0805 | C6, C7, C8, C16, C17, C18 |
| 4 | 100nF ±10% | Samsung_Electro_Mechanics_CL05B104KB54PNC:C0402 | C1, C2, C3, C13 |
| 3 | 24kΩ ±1% | UNI_ROYAL_0402WGF2402TCE:R0402 | R13, R14, R17 |
| 2 | STMicroelectronics_STPS340U:SMB_L4.6-W3.6-LS5.3-RD | D1, D2 | |
| 2 | Sunlord_SWPA8040S5R6NT:IND-SMD_L8.0-W8.0_SWPA8040S | L1, L2 | |
| 2 | Texas_Instruments_TPS54560DDAR:SOIC-8_L5.0-W4.0-P1.27-LS6.0-BL-EP2.0 | U3, U4 | |
| 2 | TWGMC_SS54:SMC_L6.9-W5.9-LS7.9-RD | D3, D4 | |
| 2 | Texas_Instruments_LM339DR:SOIC-14_L8.7-W3.9-P1.27-LS6.0-BL | U1, U2 | |
| 2 | 100kΩ ±1% | UNI_ROYAL_0402WGF1003TCE:R0402 | R15, R16 |
| 2 | 10pF ±5% | CCTC_TCC0402C0G100J500AT:C0402 | C5, C15 |
| 2 | 15kΩ ±1% | UNI_ROYAL_0402WGF1502TCE:R0402 | R1, R3 |
| 2 | 162kΩ ±1% | UNI_ROYAL_0402WGF1623TCE:R0402 | R8, R12 |
| 2 | 17.8kΩ ±1% | UNI_ROYAL_0402WGF1782TCE:R0402 | R6, R10 |
| 2 | 23.7kΩ ±1% | YAGEO_RC0402FR_0723K7L:R0402 | R5, R9 |
| 2 | 3.4kΩ ±1% | UNI_ROYAL_0402WGF3401TCE:R0402 | R7, R11 |
| 2 | 4.7nF ±5% | YAGEO_CC0402JRX7R9BB472:C0402 | C4, C14 |
| 2 | 62Ω ±1% | FOJAN_FRC0402F62R0TS:R0402 | R2, R4 |
| 1 | XKB_Connectivity_DC_005_5A_2_0:DC-IN-TH_DC-005-5A-2.0 | DC1 | |
| 1 | WCH_CH224K:ESSOP-10_L4.9-W3.9-P1.0-LS6.0-TL-EP | U5 | |
| 1 | Hubei_KENTO_Elec_Blue_light_0603:LED0603-RD | LED1 | |
| 1 | Hubei_KENTO_Elec_KT_0603R:LED0603-RD | LED10 | |
| 1 | SHOU_HAN_TYPE_C_16PIN_2MD_073:USB-C-SMD_TYPE-C-16PIN-2MD-073 | USB1 | |
| 1 | 10kΩ ±1% | UNI_ROYAL_0402WGF1002TCE:R0402 | R52 |
| 1 | 1µF ±10% | Samsung_Electro_Mechanics_CL10A105KB8NNNC:C0603 | C23 |
| 1 | 4.7kΩ ±1% | UNI_ROYAL_0402WGF4701TCE:R0402 | R18 |
Questions
How big is the Layouts PCB?
It measures 240 × 47 mm and has 2 copper layers, 1.6 mm thick.
What parts does the Layouts use?
129 parts. The full list of its parts is on this page, with links to each part's symbol and footprint where PCBKit's library has them.
Where can I download the Layouts KiCad files?
From the djmango/lightbar-dock repository on GitHub, at the commit this page was made from: the board is layouts/default/default.kicad_pcb. PCBKit opens the board in the browser, with nothing to install.
Can I use the Layouts design in my own project?
Its repository publishes it under the MIT licence: you may reuse it on that licence's terms (keep the author's notice, and for a copyleft licence share your changes alike).
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