Ngpc link sniffer

NGPC Link Cable Sniffer — KiCad project

A single passive 2-layer PCB that replaces the Neo Geo Pocket Color link cable: it wires two NGPC EXT ports together as a null-modem crossover while exposing every signal on passive tap headers for a logic analyzer or 3.3 V USB-UART adapter. No original cable required. See ../ngpc-link-sniffer-spec.md for the full design rationale.

Generated and validated with KiCad 10.0.5. DRC and ERC both pass with 0 violations.

Files

The wiring

Physical NGPC EXT pinout (identical on both consoles): 1=TXD0 2=RXD0 3=GND 4=/RTS0 5=/CTS0 — GND is the centre contact (pin 3) (see docs/reference/cable.md).

Null-modem crossover (in copper, not in the pad numbering):

SIDE A 1 TXD  ───────────── cross ───────────── 2 RXD  SIDE B
SIDE A 2 RXD  ───────────── cross ───────────── 1 TXD  SIDE B
SIDE A 3 GND  ─────────── straight ─────────── 3 GND  SIDE B
SIDE A 4 /RTS ───────────── cross ───────────── 5 /CTS SIDE B
SIDE A 5 /CTS ───────────── cross ───────────── 4 /RTS SIDE B

The two crossing pairs (TXD/RXD and /CTS//RTS) run on opposite copper layers, so they cross without shorting and without signal vias — exactly the trick the spec suggests. GND is straight on F.Cu.

Tap headers each expose their own side's five signals before the crossover, labeled TX / RX / GND / RTS / CTS. Each header pin sits directly on its signal trace (fan out to 2.54 mm, tap, fan back) — no stubs.

• TAP A (J3): SIDE A signals
• TAP B (J4): SIDE B signals

For "PC as fake console" mode (spec Scenario 2), wire a 3.3 V USB-UART to TAP A: UART TX → RX pin, UART RX → TX pin, RTS → CTS pin, CTS → RTS pin, GND → GND.

Both-face contact pads

Each of the 5 edge contacts has a pad on both F.Cu and B.Cu, tied together by a via placed inside the body at X=9 mm / X=51 mm — deliberately kept out of the pad's sliding-contact zone so there's no hole in the gold where the console spring touches.

⚠ PROVISIONAL DIMENSIONS — measure before ordering

The spec lists several EXT-port dimensions as still TBD. This board uses these placeholder values (edit scripts/gen_pcb.py and the footprint, then rerun):

Board is currently 60 mm × 24 mm, tongues 8 mm long × 11.5 mm wide (to fill the measured 12 mm slot with ~0.25 mm clearance per side), 1 mm insertion chamfers. The 6 mm pad cluster stays centred in the tongue. Overall length is arbitrary (rigid bridge between two consoles) — set it to whatever suits your bench.

Also verify with a multimeter that pin 3 (centre) = GND against the TMP95C061 SIO0 pins on the mainboard, and confirm the left-to-right pad order and which board face the port contacts, before committing to fab. This is why pads are on both faces and why the revision is v0.1.

Ordering

• Layers: 2 · Copper: 1 oz · Min trace: 0.3 mm (0.2 mm rules)
• Order both 0.8 mm and 1.0 mm thickness (slot measured 1.0–1.5 mm)
• Surface finish: ENIG (gold) for the wear-resistant contact pads
• Solder mask is already opened over all contact pads
• Upload gerbers/ to JLCPCB / OSHPark / PCBWay

Regenerating

# PCB (needs KiCad's bundled python / pcbnew):
flatpak run --command=python3 org.kicad.KiCad scripts/gen_pcb.py
# Schematic (plain python3):
python3 scripts/gen_sch.py
# Validate:
flatpak run --command=kicad-cli org.kicad.KiCad pcb drc  ngpc-link-sniffer.kicad_pcb
flatpak run --command=kicad-cli org.kicad.KiCad sch erc  ngpc-link-sniffer.kicad_sch

License

MIT / CERN-OHL-P (permissive open hardware).