Switch main v4

Switch v4 Hardware

KiCad design files for the 4th iteration of my single pair Ethernet (SPE) switch. The firmware can be found in unified-switch-firmware.

Also see my post on r/embedded!

Design

See the schematic for a block diagram and in-depth details.

The main switch chip is an SJA1105QEL from NXP. It is configured via SPI by an STM32H573IIK3Q. The STM32 is also connected by reduced media independent interface (RMII) to the switch so it is able to send and receive management traffic such as Spanning Tree Protocol (STP) BPDUs as well as Precision Time Protocol (PTP) packets and diagnostic information.

The connections for each SJA1105 port are shown below:

PoDL PSE

Power over Datalines (PoDL) is similar to Power over Ethernet (PoE) but for SPE. In regular PoE power is sent over the center taps of the transformers, however in SPE there is only one (or no) transformer so this wouldn't work. Instead, DC power is injected into the datalines in the Coupling Decoupling Network (CDN) using differential mode inductors (DMI). The switch is only capable of being a Power Sourcing Equipment (PSE) which powers other devices. It must get its own power through the other connectors on the board.

PoDL has been implemented on ports 1, 2 and 3 of the switch.

• Ports 1 and 2 are able to output 1.1A each and use a simple detection method before supplying power to a load. Firstly ~14mA is sent down the cable, then if the bus voltage is between 4.05 and 4.55V then the full supply is enabled (typically 24V). This is usually done by a zener diode on the other end of the cable.

• Port 3 is also able to output 1.1A and uses a custom multidrop PoDL implementation. Detection is done by powering the bus at 6.5V, then each device on the bus draws 1mA for every 1W of power they want. Then the full supply is enabled.

An STM32H503KBU6 is used as a secondary processor to control the PoDL operations. It talks to the primary processor via UART through an optocoupler. This means the data and power circuits are galvanically isolated.

Test Rig

The test rig PCB is designed so that its pogo pins align directly with the test pads on the bottom of the main switch board. This means a debugger can be connected without needing to include a header on the main board.

Versions

See the errata for details on bugs.

References

Datasheets:

• 88Q2112 Datasheet (requires an Infineon account)
• SJA1105 Datasheet
• LAN8671 Datasheet

PoDL:

• How to Implement an IEEE 802.3cg or 802.3bu-Compliant PoDL PSE - TI
• 1000BASE-T1 PoDL Reference design - TI
• PSE Schematic - TI
• IEEE 802.3cg 10BASE-T1L Power over Data Lines Powered Device Design - TI
  • References non-existent inductors :/
• SINGLE PAIR ETHERNET FILTER DESIGN - WE
• Power Injection Inductors for 10BASE-T1 PoDL - Coilcraft
• 10BASE-T1L Converter w/ PoE+PoDL