Bebop mb

Bebop Motherboard (bebop-mb)

KiCad 10 project for the Bebop Connector / motherboard board. It is the interconnect between an NVIDIA Jetson Orin Nano carrier board, a Teensy 4.1 microcontroller, a Bosch BNO085 9‑DoF IMU (Adafruit breakout), and a CAN bus front end. The board mostly provides headers/breakouts and routes shared buses between these modules.

Silkscreen title block: "Bebop Connector".

Schematic sheets

Component / connector reference

Power rails

The Jetson 40‑pin header also exposes its own 3.3V (pins 1, 17) and 5.0V (pins 2, 4) on J9/J10; these are not tied to the board +3.3V rail unless you bridge them.

Teensy 4.1 (U1) → breakouts J6 / J7

J6/J7 are 1×24 socket breakouts; J6 pad N = Teensy pin N, J7 pad N = Teensy pin N+24. Silkscreen on J6/J7 shows the Teensy pin name.

Active Teensy connections

IMU_SCL/IMU_SDA are the legacy I²C pins. The IMU was migrated to SPI, so these are now just an unused I²C bus broken out on J7.

BNO085 IMU (J8) — wired for SPI

The BNO085 is configured for SPI (not I²C). Protocol is selected by tying P0/P1 high.

J11 breaks out the primary row (VIN/3Vo/GND/SCL/SDA/INT) and J12 the secondary row (BT/P0/P1/RST/DI/CS); both simply follow whatever J8 carries.

Shared IMU SPI bus (Teensy and Jetson)

The BNO085 SPI bus is wired in parallel to both the Teensy and the Jetson so either can act as master. They must not be active at the same time.

            IMU_SCK / IMU_MISO / IMU_MOSI / IMU_CS / IMU_INT / IMU_RST
                                  |
        +---------------+---------+---------+----------------+
        |               |                   |                |
   BNO085 (J8)     Teensy U1           Jetson J5         Breakouts
                (13/12/11/10,        (SPI0 + GPIO,      (J6/J7, J9/J10,
                 37/36)               see below)         J11/J12)

⚠️ Bus contention: there is no hardware isolation (no mux/buffer) between the two masters. Firmware must keep the inactive master's SCK/MOSI/CS (and INT/RST) pins as high‑impedance inputs so the two masters never drive the bus simultaneously.

Jetson 40‑pin header (J5) → breakouts J9 / J10

J5 is a 2×20 IDC box header (ribbon to the Jetson carrier 40‑pin expansion header). J9 breaks out the odd column, J10 the even column. Silkscreen on J9/J10 is <Jetson pin #> <signal>.

Pins in bold are routed to the shared IMU bus; all other pins are simply broken out on J9/J10 for access.

CAN bus (U2 + J1–J4)

U2 (SN65HVD230, 3.3 V) bridges the Teensy CAN1 controller to the physical bus.

• J1 — 3‑pin screw terminal: CANH / CANL / GND.
• J2, J3, J4 — JST‑GH 2‑pin: CANH / CANL (for daisy‑chaining nodes).

Add a 120 Ω termination resistor at the bus ends as needed (not currently populated on‑board).

Notes

• This board is KiCad 10 (name‑based nets; no numbered net table).
• After editing any schematic sheet, run Tools → Update PCB from Schematic and re‑run DRC.
• The IMU SPI bus sharing relies on firmware discipline (see the contention warning above); if you want hardware‑guaranteed isolation, add series resistors or a GPIO/jumper‑selected SPI bus switch.